MSCAN08 Controller (MSCAN08)
Technical Data
MC68HC08AZ32A — Rev 1.0
366
MSCAN08 Controller (MSCAN08)
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MOTOROLA
aborted due to a pending abort request (see
Transmit Buffer
Priority Registers
on page 352). If not masked, a receive interrupt is
pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag
(ABTAK, see above). When a TXEx flag is set, the corresponding
ABTRQx bit (ABTRQ, see
MSCAN08 Transmitter Control Register
)
is cleared.
1 = The associated message buffer is empty (not scheduled).
0 = The associated message buffer is full (loaded with a message
due for transmission).
NOTE:
To ensure data integrity, no registers of the transmit buffers should be
written to while the associated TXE flag is cleared.
NOTE:
The CTFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
20.14.8 MSCAN08 Transmitter Control Register
ABTRQ2–ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that an already scheduled
message buffer (TXE = 0) be aborted. The MSCAN08 will grant the
request if the message has not already started transmission, or if the
transmission is not successful (lost arbitration or error). When a
message is aborted the associated TXE and the abort acknowledge
flag (ABTAK) (see
MSCAN08 Transmitter Flag Register
on page
Address:
$0507
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
ABTRQ2
ABTRQ1
ABTRQ0
0
TXEIE2
TXEIE1
TXEIE0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-22. Transmitter Control Register (CTCR)
F
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n
.