Timer Interface Module A (TIMA)
Technical Data
MC68HC08AZ32A — Rev 1.0
384
Timer Interface Module A (TIMA)
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MOTOROLA
Figure 22-2. TIMA I/O Register Summary
Addr.
Register Name
Bit 7
TOF
0
Bit 15
R
Bit 7
R
6
5
4
0
3
0
R
11
R
3
R
2
1
Bit 0
$0020
TIMA Status/Control Register (TASC)
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
R:
W:
TOIE
TSTOP
PS2
PS1
PS0
TRST
12
R
4
R
$0022
TIMA Counter Register High (TACNTH)
14
R
6
R
13
R
5
R
10
R
2
R
9
R
1
R
Bit 8
R
Bit 0
R
$0023
TIMA Counter Register Low (TACNTL)
$0024
TIMA Counter Modulo Reg. High
(TAMODH)
Bit 15
14
13
12
11
10
9
Bit 8
$0025
TIMA Counter Modulo Reg. Low
(TAMODL)
Bit 7
6
5
4
3
2
1
Bit 0
$0026
TIMA Ch. 0 Status/Control Register
(TASC0)
CH0F
0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
$0027
TIMA Ch. 0 Register High (TACH0H)
Bit 15
14
13
12
11
10
9
Bit 8
$0028
TIMA Ch. 0 Register Low (TACH0L)
Bit 7
6
5
4
3
2
1
Bit 0
$0029
TIMA Ch. 1 Status/Control Register
(TASC1)
CH1F
0
CH1IE
0
R
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
$002A
TIMA Ch. 1 Register High (TACH1H)
Bit 15
14
13
12
11
10
9
Bit 8
$002B
TIMA Ch. 1 Register Low (TACH1L)
Bit 7
6
5
4
3
2
1
Bit 0
$002C
TIMA Ch. 2 Status/Control Register
(TASC2)
CH2F
0
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
$002D
TIMA Ch. 2 Register High (TACH2H)
Bit 15
14
13
12
11
10
9
Bit 8
$002E
TIMA Ch. 2 Register Low (TACH2L)
Bit 7
6
5
4
3
2
1
Bit 0
$002F
TIMA Ch. 3 Status/Control Register
(TASC3)
CH3F
0
CH3IE
0
R
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
$0030
TIMA Ch. 3 Register High (TACH3H)
Bit 15
14
13
12
11
10
9
Bit 8
$0031
TIMA Ch. 3 Register Low (TACH3L)
Bit 7
6
5
4
3
2
1
Bit 0
F
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