
Memory Map
Additional Status and Control Registers
MC68HC08AZ32A — Rev 1.0
Technical Data
MOTOROLA
Memory Map
49
2.4 Additional Status and Control Registers
Selected addresses in the range $FE00 to $FFCB contain additional
Status and Control registers as shown in
Figure 2-3
. A noted exception
is the COP Control Register (COPCTL) at address $FFFF.
Addr.
$FE00
SIM Break Status Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
(SBSR)
R:
W:
R:
W:
R:
W:
R:EEK
R
R
R
R
R
R
BW
0
LVI
R
$FE01
SIM Reset Status Register
(SRSR)
POR
PIN
COP
ILOP
ILAD
0
0
$FE03
SIM Break Flag Control
Register (SBFCR)
BCFE
R
R
R
R
R
R
R
$FE09
Mask Option Register B
(MORB)
R
R
EESEC
EEMONSE
C
R
AZ32A
R
R
R
W:
R:
W:
R:
W:
R:
W:
R: LVIOUT
W:
R:
W:
SECD
R:
W:
EEDIV7
R:
W:
SECD
R:
W:
EEDIV7
R:
W:
R:
W:
R:
W:
R:
W:
R
R
$FE0C
Break Address Register
High (BRKH)
Break Address Register
Low (BRKL)
Break Status and Control
Register (BRKSCR)
Bit 15
14
13
12
11
10
9
8
$FE0D
7
6
5
4
3
2
1
0
$FE0E
BRKE
BRKA
0
0
0
0
0
0
$FE0F
LVI Status Register (LVISR)
0
0
0
0
0
0
0
$FE10
EEDIV High Non-volatile
Register (EEDIVHNVR)
EEDIV Low Non-volatile
Register (EEDIVLNVR)
EEDIV Divider High
Register
(EEDIVH)
EEDIV Divider Low
Register
(EEDIVL)
EEDIV
R
R
R
R
EEDIV10 EEDIV9
EEDIV8
$FE11
EEDIV6
EEDIV5
EEDIV4
EEDIV3
EE2DIV
EEDIV1
EEDIV0
$FE1A
EEDIV
0
0
0
0
EEDIV10 EEDIV9
EEDIV8
$FE1B
EEDIV6
EEDIV5
EEDIV4
EEDIV3
EE2DIV
EEDIV1
EEDIV0
$FE1C
EENVR
R
R
R
EEPRTCT
EEPB3
EEPB2
EEPB1
EEPB0
$FE1D
EECR
R
0
EEOFF
EERAS1
EERAS0
ELAT
AUTO
EEPGM
$FE1F
EEACR
R
R
R
EEPRTCT
EEBP3
EEBP2
EEBP1
EEBP0
$FFFF
COP Control Register
(COPCTL)
LOW BYTE OF RESET VECTOR
WRITING TO $FFFF CLEARS COP COUNTER
= Unimplemented
R
= Reserved
Figure 2-3. Additional Status and Control Registers
F
Freescale Semiconductor, Inc.
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n
.