Timer Interface Module A (TIMA)
I/O Registers
MC68HC08AZ32A — Rev 1.0
Technical Data
MOTOROLA
Timer Interface Module A (TIMA)
For More Information On This Product,
Go to: www.freescale.com
397
prescaler select bits, PS[2:0] (see TIMA Status and Control Register).
The minimum TCLK pulse width, TCLK
LMIN
or TCLK
HMIN
, is:
1
bus frequency
The maximum TCLK frequency is the least: 4 MHz or bus frequency
÷
2.
PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIMA clock input. When the
PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless
of the state of the DDRD6 bit in data direction register D.
22.8.2 TIMA Channel I/O Pins (PTF3/TACH5–PTF0/TACH2 and
PTE3/TACH1–PTE2/TACH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TACH0, PTF0/TACH2 and
PTF2/TACH4 can be configured as buffered output compare or buffered
PWM pins.
22.9 I/O Registers
These I/O registers control and monitor TIMA operation:
TIMA status and control register (TASC)
TIMA control registers (TACNTH–TACNTL)
TIMA counter modulo registers (TAMODH–TAMODL)
TIMA channel status and control registers (TASC0, TASC1,
TASC2, TASC3, TASC4 and TASC5)
TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L,
TACH2H–TACH2L, TACH3H–TACH3L, TACH4H–TACH4L and
TACH5H–TACH5L)
-------------------------------------
t
SU
+
F
Freescale Semiconductor, Inc.
n
.