I/O Ports
Technical Data
MC68HC08AZ32A — Rev 1.0
294
I/O Ports
MOTOROLA
19.2 Introduction
Fifty bidirectional input-output (I/O) pins form eight parallel ports. All I/O
pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either V
DD
or
V
SS
. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Table 19-1. I/O Port Register Summary
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Addr.
Port A Data Register (PTA)
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0000
Port B Data Register (PTB)
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
$0001
Port C Data Register (PTC)
R:
W:
0
R
0
R
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0 $0002
Port D Data Register (PTD)
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0 $0003
Data Direction Register A (DDRA)
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004
Data Direction Register B (DDRB)
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005
Data Direction Register C (DDRC)
R:
MCLKEN
W:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 $0007
0
R
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 $0006
Data Direction Register D (DDRD)
Port E Data Register (PTE)
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
$0008
Port F Data Register (PTF)
R:
W:
R:
W:
R:
W:
0
R
0
R
0
R
PTF6
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
$0009
Port G Data Register (PTG)
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
PTG2
PTG1
PTG0 $000A
Port H Data Register (PTH)
0
R
PTH1
PTH0 $000B
Data Direction Register E (DDRE)
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 $000C
Data Direction Register F (DDRF)
R:
W:
0
R
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 $000D
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.