
Serial Peripheral Interface (SPI)
Technical Data
MC68HC08AZ32A — Rev 1.0
228
Serial Peripheral Interface (SPI)
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MOTOROLA
16.12.3 SPSCK (Serial Clock)
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
249
16.12.4 SS (Slave Select)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
250
16.12.5 VSS (Clock Ground)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
251
16.13 I/O Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
251
16.13.1 SPI Control Register (SPCR)
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252
16.13.2 SPI Status and Control Register (SPSCR)
. . . . . . . . . . .
254
16.13.3 SPI Data Register (SPDR)
. . . . . . . . . . . . . . . . . . . . . . . .
258
16.2 Introduction
This section describes the serial peripheral interface module (SPI),
which allows full-duplex, synchronous, serial communications with
peripheral devices.
16.3 Features
Features of the SPI module include the following:
Full-duplex operation
Master and slave modes
Double-buffered operation with separate transmit and receive
registers
Four master mode frequencies (maximum = bus frequency
÷
2)
Maximum slave mode frequency = bus frequency
Serial clock with programmable polarity and phase
Two separately enabled interrupts with CPU service:
–
SPRF (SPI receiver full)
–
SPTE (SPI transmitter empty)
Mode fault error flag with CPU interrupt capability
Overflow error flag with CPU interrupt capability
Programmable wired-OR mode
I
2
C (inter-integrated circuit) compatibility
F
Freescale Semiconductor, Inc.
n
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