
Clock Generator Module (CGM)
CGM Registers
MC68HC08AZ32A — Rev 1.0
Technical Data
MOTOROLA
Clock Generator Module (CGM)
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135
To check the status of the crystal reference, do the following:
1. Write a logic 1 to XLD.
2. Wait N
×
4 cycles. N is the VCO frequency multiplier.
3. Read XLD.
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
Bits 3–0 — Reserved for Test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write 0s to bits 3–0 when writing to PBWC.
8.6.3 PLL Programming Register
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See
Circuits
on page 121 and
Programming the PLL
on page 125). A value of $0 in the multiplier
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
Write:
Reset:
0
1
1
0
0
1
1
0
Figure 8-6. PLL Programming Register (PPG)
F
Freescale Semiconductor, Inc.
n
.