參數(shù)資料
型號(hào)： ZL50119GAG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： 32, 64 and 128 Channel CESoP Processors
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA324
封裝： 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324
文件頁(yè)數(shù)： 59/95頁(yè)
文件大?。?/td> 1157K
代理商： ZL50119GAG
ZL50115/16/17/18/19/20
Data Sheet
59
Zarlink Semiconductor Inc.
8.8 Miscellaneous Features
System clock speed of 100 MHz
Host clock speed of up to 66 MHz
Debug option to freeze all internal state machines
JTAG (IEEE1149) Test Access Port
3.3 V I/O Supply rail with 5 V tolerance
1.8 V Core Supply rail
Fully compatible with MT90880/1/2/3 and ZL50110/11/14 Zarlink product line
8.9 Test Modes Operation
8.9.1 Overview
The ZL5011x family supports the following modes of operation.
8.9.1.1 System Normal Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
8.9.1.2 System Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
8.9.2 Test Mode Control
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 23.
8.9.3 System Normal Mode
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of
the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
8.9.4 System Tri-state Mode
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
System Test Mode
test_mode[2:0]
SYS_NORMAL_MODE
3’b000
SYS_TRI_STATE_MODE
3’b011
Table 23 - Test Mode Control
相關(guān)PDF資料
PDF描述
ZL50120GAG 32, 64 and 128 Channel CESoP Processors
ZL50118GAG Connector assemblies, Network cables;
ZL50117GAG REFLECTIVE PHOTOSENSOR SMD RSS42
ZL50115 32, 64 and 128 Channel CESoP Processors
ZL50116 32, 64 and 128 Channel CESoP Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50119GAG2 制造商:Microsemi Corporation 功能描述:64 CHANNEL CESOP PROCESSOR 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 324BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA
ZL50120 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors
ZL50120GAG 制造商:Microsemi Corporation 功能描述:CH CESOP PROCESSORS 324BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 324PBGA
ZL50120GAG2 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 324BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 324PBGA
ZL50130 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Ethernet Pseudo-Wires across a PSN
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