參數(shù)資料
型號(hào)： ZL50115
廠商： Zarlink Semiconductor Inc.
英文描述： 32, 64 and 128 Channel CESoP Processors
中文描述： 32，64和128頻道CESoP處理器
文件頁數(shù)： 1/95頁
文件大?。?/td> 1157K
代理商： ZL50115
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
General
Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
On chip timing & synchronization recovery across
a packet network
On chip dual reference Stratum 3 DPLL
Grooming capability for Nx64 Kbps trunking
Fully compatible with Zarlink's ZL50110, ZL50111
and ZL50114 CESoP processors
Circuit Emulation Services
Complies with ITU-T recommendation Y.1413
Complies with IETF PWE3 draft standards
CESoPSN and SAToP
Complies with CESoP Implementation
Agreements from MEF 8 and MFA 8.0.0
Structured, synchronous CESoP with clock
recovery
Unstructured, asynchronous CESoP with integral
per-stream clock recovery
Customer Side TDM Interfaces
Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
H.110, H-MVIP, ST-BUS backplane
Up to 128 bi-directional 64 Kbps channels
Direct connection to LIUs, framers, backplanes
Customer Side Packet Interfaces
100 Mbps MII Fast Ethernet (ZL50118/19/20 only)
(may also be used as a second provider side packet
interface)
Provider Side Packet Interfaces
100 Mbps MII Fast Ethernet or 1000 Mbps
GMII/TBI Gigabit Ethernet
April 2005
Ordering Information
ZL50115GAG 324 Ball PBGA
ZL50116GAG 324 Ball PBGA
ZL50117GAG 324 Ball PBGA
ZL50118GAG 324 Ball PBGA
ZL50119GAG 324 Ball PBGA
ZL50120GAG 324 Ball PBGA
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
-40
°
C to +85
°
C
ZL50115/16/17/18/19/20
32, 64 and 128 Channel CESoP
Processors
Data Sheet
Figure 1 - ZL50115/16/17/18/19/20 High Level Overview
On Chip Packet Memory
(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)
Dual Reference
Stratum 3 DPLL
Host Processor
Interface
JTAG
4
H
1
F
1
o
1
B
C
32-bit Motorola compatible
DMA for signaling packets
Multi-Protocol
Packet
Processing
Engine
PW, RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
Defined, Others
Dual
Packet
Interface
MAC
(MII, GMII, TBI)
TDM
Interface
(LIU, Framer, Backplane)
Per Port DCO for
Clock Recovery
相關(guān)PDF資料
PDF描述
ZL50116 32, 64 and 128 Channel CESoP Processors
ZL50117 32, 64 and 128 Channel CESoP Processors
ZL50118 32, 64 and 128 Channel CESoP Processors
ZL50119 32, 64 and 128 Channel CESoP Processors
ZL50120 32, 64 and 128 Channel CESoP Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50115GAG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA
ZL50115GAG2 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA
ZL50116 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors
ZL50116GAG 制造商:Microsemi Corporation 功能描述:2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA
ZL50116GAG2 制造商:Microsemi Corporation 功能描述:PB FREE 2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA
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