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參數(shù)資料
| 型號： | ZL50115 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 32, 64 and 128 Channel CESoP Processors |
| 中文描述： | 32，64和128頻道CESoP處理器 |
| 文件頁數(shù)： | 85/95頁 |
| 文件大小： | 1157K |
| 代理商： | ZL50115 |
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ZL50115/16/17/18/19/20
Data Sheet
85
Zarlink Semiconductor Inc.
12.8 System Function Port
Note 1:
The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a
short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature
coefficient of 0.1 ppm/oC, a 10oC change in temperature while the DPLL is in will result in a frequency accuracy offset of
1 ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
Note 2:
The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e., frequency of clock output
equals 8.192 MHz ± SYSTEM_CLK accuracy ± 0.005 ppm).
Note 3:
The absolute SYSTEM_CLK accuracy must be controlled to ± 30 ppm in synchronous master mode to enable the internal
DPLL to function correctly.
Note 4:
In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may
be relaxed slightly.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
SYSTEM_CLK Frequency
CLK
FR
-
100
-
MHz
Note 1 and Note
2
SYSTEM_CLK accuracy
(synchronous master mode)
CLK
ACS
-
-
±30
ppm
Note 3
SYSTEM_CLK accuracy
(synchronous slave mode and
asynchronous mode)
CLK
ACA
-
-
±200
ppm
Note 4
Table 37 - System Clock Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50116GAG | 制造商:Microsemi Corporation 功能描述:2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
| ZL50116GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
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