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參數(shù)資料
| 型號(hào)： | ZL50115 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 32, 64 and 128 Channel CESoP Processors |
| 中文描述： | 32，64和128頻道CESoP處理器 |
| 文件頁(yè)數(shù)： | 36/95頁(yè) |
| 文件大?。?/td> | 1157K |
| 代理商： | ZL50115 |
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ZL50115/16/17/18/19/20
Data Sheet
36
Zarlink Semiconductor Inc.
CPU_CS
I U
N21
CPU Chip Select. Synchronous to rising
edge of CPU_CLK and active low. Is
asserted with CPU_TS_ALE. Must be
asserted with CPU_OE to
asynchronously enable the CPU_DATA
output during a read, including DMA
read.
CPU_WE
I
M21
CPU Write Enable. Synchronously
asserted with respect to CPU_CLK
rising edge, and active low. Used for
CPU writes from the processor to
registers within the ZL5011x. Asserted
one clock cycle after CPU_TS_ALE.
CPU_OE
I
M22
CPU Output Enable.
Synchronously asserted with respect to
CPU_CLK rising edge, and active low.
Used for CPU reads from the processor
to registers within the ZL5011x.
Asserted one clock cycle after
CPU_TS_ALE. Must be asserted with
CPU_CS to asynchronously enable the
CPU_DATA output during a read,
including DMA read.
CPU_TS_ALE
I
M20
Synchronous input with rising edge of
CPU_CLK.
Latch Enable (ALE), active high signal.
Asserted with CPU_CS, for a single
clock cycle.
CPU_SDACK1
I
A21
CPU/DMA 1 Acknowledge Input. Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL5011x for a DMA write
transaction. Only used for DMA
transfers, not for normal register access.
CPU_SDACK2
I
L21
CPU/DMA 2 Acknowledge Input Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL5011x for a DMA read
transaction. Only used for DMA
transfers, not for normal register access.
CPU_CLK
I
L19
CPU PowerQUICC II Bus Interface
clock input. 66 MHz clock, with minimum
of 6 ns high/low time. Used to time all
host interface signals into and out of
ZL5011x device.
Signal
I/O
Package Balls
Description
Table 10 - CPU Interface Package Ball Definition (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50116 | 32, 64 and 128 Channel CESoP Processors |
| ZL50117 | 32, 64 and 128 Channel CESoP Processors |
| ZL50118 | 32, 64 and 128 Channel CESoP Processors |
| ZL50119 | 32, 64 and 128 Channel CESoP Processors |
| ZL50120 | 32, 64 and 128 Channel CESoP Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50116GAG | 制造商:Microsemi Corporation 功能描述:2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
| ZL50116GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
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