- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373786 > ZL50120GAG (ZARLINK SEMICONDUCTOR INC) 32, 64 and 128 Channel CESoP Processors PDF資料下載
參數(shù)資料
| 型號： | ZL50120GAG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 32, 64 and 128 Channel CESoP Processors |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA324 |
| 封裝： | 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324 |
| 文件頁數(shù)： | 1/95頁 |
| 文件大?。?/td> | 1157K |
| 代理商： | ZL50120GAG |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
General
Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
On chip timing & synchronization recovery across
a packet network
On chip dual reference Stratum 3 DPLL
Grooming capability for Nx64 Kbps trunking
Fully compatible with Zarlink's ZL50110, ZL50111
and ZL50114 CESoP processors
Circuit Emulation Services
Complies with ITU-T recommendation Y.1413
Complies with IETF PWE3 draft standards
CESoPSN and SAToP
Complies with CESoP Implementation
Agreements from MEF 8 and MFA 8.0.0
Structured, synchronous CESoP with clock
recovery
Unstructured, asynchronous CESoP with integral
per-stream clock recovery
Customer Side TDM Interfaces
Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
H.110, H-MVIP, ST-BUS backplane
Up to 128 bi-directional 64 Kbps channels
Direct connection to LIUs, framers, backplanes
Customer Side Packet Interfaces
100 Mbps MII Fast Ethernet (ZL50118/19/20 only)
(may also be used as a second provider side packet
interface)
Provider Side Packet Interfaces
100 Mbps MII Fast Ethernet or 1000 Mbps
GMII/TBI Gigabit Ethernet
April 2005
Ordering Information
ZL50115GAG 324 Ball PBGA
ZL50116GAG 324 Ball PBGA
ZL50117GAG 324 Ball PBGA
ZL50118GAG 324 Ball PBGA
ZL50119GAG 324 Ball PBGA
ZL50120GAG 324 Ball PBGA
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
-40
°
C to +85
°
C
ZL50115/16/17/18/19/20
32, 64 and 128 Channel CESoP
Processors
Data Sheet
Figure 1 - ZL50115/16/17/18/19/20 High Level Overview
On Chip Packet Memory
(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)
Dual Reference
Stratum 3 DPLL
Host Processor
Interface
JTAG
4
H
1
F
1
o
1
B
C
32-bit Motorola compatible
DMA for signaling packets
Multi-Protocol
Packet
Processing
Engine
PW, RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
Defined, Others
Dual
Packet
Interface
MAC
(MII, GMII, TBI)
TDM
Interface
(LIU, Framer, Backplane)
Per Port DCO for
Clock Recovery
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50118GAG | Connector assemblies, Network cables; |
| ZL50117GAG | REFLECTIVE PHOTOSENSOR SMD RSS42 |
| ZL50115 | 32, 64 and 128 Channel CESoP Processors |
| ZL50116 | 32, 64 and 128 Channel CESoP Processors |
| ZL50117 | 32, 64 and 128 Channel CESoP Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50120GAG2 | 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 324BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 324PBGA |
| ZL50130 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Ethernet Pseudo-Wires across a PSN |
| ZL50130GAG | 制造商:Microsemi Corporation 功能描述:ETHERNET PSEUDO-WIRES 384BGA - Trays |
| ZL50130PBGA | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Ethernet Pseudo-Wires across a PSN |
| ZL50211 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:256 Channel Voice Echo Canceller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。