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參數(shù)資料
| 型號： | ZL50120GAG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 32, 64 and 128 Channel CESoP Processors |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA324 |
| 封裝： | 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324 |
| 文件頁數(shù)： | 53/95頁 |
| 文件大?。?/td> | 1157K |
| 代理商： | ZL50120GAG |
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ZL50115/16/17/18/19/20
Data Sheet
53
Zarlink Semiconductor Inc.
6.4.1.1 Payload Order
Packets are assembled sequentially, with each channel placed into the packet as it arrives at the TDM
Interface. A fixed order of channels is maintained (see Figure 18), with channel 0 placed before channel 1,
which is placed before channel 2. It is this order that allows the packet to be correctly disassembled at the far
end. A context must contain only unique channel numbers. As such a context that contains the same channel
from different streams, for example channel 1 from stream 2 and channel 1 from stream 3, would not be
permitted.
Figure 18 - Channel Order for Packet Formation
Each packet contains one or more frames of TDM data, in sequential order. This groups the selected channels
for the first frame, followed by the same set of channels for the subsequent frame, and so on.
6.4.2 Unstructured Payload Operation
In unstructured mode, the payload is not split by defined frames or timeslots, so the packet consists of a continuous
stream of data. Each packet consists of a number of octets, as shown in Figure 19. The number of octets in a
packet need not be an integer number of frames. A typical value for N may be 192, as defined in the IETF PWE3
standard."
For example, consider mapping the unstructured data of a 25 timeslot DS0 stream. The data for each T1 frame
would normally consist of 193 bits, 192 data bits and 1 framing bit. If the payload consists of 24 octets it will be 1 bit
short of a complete frames worth of data, if the payload consists of 25 octets it will be 7 bits over a complete frames
worth of data.
NOTE:
No alignment of the octets with the T1 framing structure can be assumed.
Figure 19 - ZL50115/16/17/18/19/20 Packet Format - Unstructured Mode
Channel 0
Channel 1
Channel 2
Channel 31
Stream 0
Channel 0
Channel 1
Channel 2
Channel 31
Stream 3
Channel 0
Channel 1
Channel 2
Channel 31
Stream 1
Channel 0
Channel 1
Channel 2
Channel 31
Stream 2
Channel Assembly Order
Header
N octets of data from unstructured stream
NOTE:
No frame or channel alignment
may include VLAN tagging
e.g. IPv4, IPv6, MPLS
e.g. UDP, L2TP, RTP,
CESoPSN, SAToP
TDM Payload
(constructed by Payload Assembler)
46 to 1500 bytes
may also be placed in the
packet header
Octet 1
Octet 2
Octet N
Static Padding
Ethernet Header
Network Layers
(added by Packet Transmit)
Upper layers
(added by Protocol Engine)
Ethernet FCS
(if required to meet minimum payload size)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50118GAG | Connector assemblies, Network cables; |
| ZL50117GAG | REFLECTIVE PHOTOSENSOR SMD RSS42 |
| ZL50115 | 32, 64 and 128 Channel CESoP Processors |
| ZL50116 | 32, 64 and 128 Channel CESoP Processors |
| ZL50117 | 32, 64 and 128 Channel CESoP Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50120GAG2 | 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 324BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 324PBGA |
| ZL50130 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Ethernet Pseudo-Wires across a PSN |
| ZL50130GAG | 制造商:Microsemi Corporation 功能描述:ETHERNET PSEUDO-WIRES 384BGA - Trays |
| ZL50130PBGA | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Ethernet Pseudo-Wires across a PSN |
| ZL50211 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:256 Channel Voice Echo Canceller |
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