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參數(shù)資料
| 型號： | ZL50120GAG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 32, 64 and 128 Channel CESoP Processors |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA324 |
| 封裝： | 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324 |
| 文件頁數(shù)： | 38/95頁 |
| 文件大小： | 1157K |
| 代理商： | ZL50120GAG |
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ZL50115/16/17/18/19/20
Data Sheet
38
Zarlink Semiconductor Inc.
4.5 System Function Interface
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock.
4.6 Test Facilities
4.6.1 Administration, Control and Test Interface
All Administration, Control and Test Interface signals are 5 V tolerant.
Signal
I/O
Package Balls
Description
SYSTEM_CLK
I
W13
System Clock Input. The system clock
frequency is 100 MHz. The frequency
must be accurate to within ±32 ppm in
synchronous mode.
SYSTEM_RST
I
AA12
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the /1/4 to be
reset to their default state.
SYSTEM_DEBUG
I
AA11
System Debug Enable. This is an
asynchronous
signal
de-asserted,
prevents
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high.
that,
the
when
software
Table 11 - System Function Interface Package Ball Definition
Signal
I/O
Package Balls
Description
GPIO[15:0]
ID/
OT
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
W17
Y16
AB16
AA16
AB15
AB14
W15
Y15
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AA15
AB13
AB12
AB11
AB10
AA14
AA13
AB9
General Purpose I/O pins. Connected to an
internal register, so customer can set
user-defined parameters. Bits [4:0] reserved
at start-up or reset for memory TDL setup.
See the ZL50115/16/17/18/19/20
Programmers Model for more details.
Recommend 5 kohm pulldown on these
signals.
TEST_MODE[2:0]
I D
[2]
[1]
[0]
AB17
Y17
AA17
Test Mode input - ensure these pins are tied
to ground for normal operation.
000 SYS_NORMAL_MODE
001-010 RESERVED
011 SYS_TRISTATE_MODE
100-111 RESERVED
Table 12 - Administration/Control Interface Package Ball Definition
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ZL50120GAG2 | 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 324BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 324PBGA |
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| ZL50130GAG | 制造商:Microsemi Corporation 功能描述:ETHERNET PSEUDO-WIRES 384BGA - Trays |
| ZL50130PBGA | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Ethernet Pseudo-Wires across a PSN |
| ZL50211 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:256 Channel Voice Echo Canceller |
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