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ZL50115/16/17/18/19/20
Data Sheet
19
Zarlink Semiconductor Inc.
B9
M0_RBC0
M0_RBC0
M0_RBC0
M0_RBC0
M0_RBC0
M0_RBC0
All
C1
NC
NC
NC
M1_TXD[3]
M1_TXD[3]
M1_TXD[3]
ZL50118/19/20
C10
M0_RXCLK
M0_RXCLK
M0_RXCLK
M0_RXCLK
M0_RXCLK
M0_RXCLK
All
C11
M0_TXD[7]
M0_TXD[7]
M0_TXD[7]
M0_TXD[7]
M0_TXD[7]
M0_TXD[7]
All
C12
M0_TXD[4]
M0_TXD[4]
M0_TXD[4]
M0_TXD[4]
M0_TXD[4]
M0_TXD[4]
All
C13
M0_TXD[0]
M0_TXD[0]
M0_TXD[0]
M0_TXD[0]
M0_TXD[0]
M0_TXD[0]
All
C14
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
C15
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
C16
CPU_DATA[31]
CPU_DATA[31]
CPU_DATA[31]
CPU_DATA[31]
CPU_DATA[31]
CPU_DATA[31]
All
C17
NC
NC
NC
M1_LINKUP_LED
M1_LINKUP_LED
M1_LINKUP_LED
ZL50118/19/20
C18
CPU_DATA[29]
CPU_DATA[29]
CPU_DATA[29]
CPU_DATA[29]
CPU_DATA[29]
CPU_DATA[29]
All
C19
CPU_DATA[26]
CPU_DATA[26]
CPU_DATA[26]
CPU_DATA[26]
CPU_DATA[26]
CPU_DATA[26]
All
C20
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
C21
GND
GND
GND
GND
GND
GND
All
C22
CPU_DREQ1
CPU_DREQ1
CPU_DREQ1
CPU_DREQ1
CPU_DREQ1
CPU_DREQ1
All
C2
GND
GND
GND
GND
GND
GND
All
C3
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
C4
NC
NC
NC
M1_RXCLK
M1_RXCLK
M1_RXCLK
ZL50118/19/20
C5
NC
NC
NC
M1_COL
M1_COL
M1_COL
ZL50118/19/20
C6
NC
NC
NC
M1_TXER
M1_TXER
M1_TXER
ZL50118/19/20
C7
M0_RXDV
M0_RXDV
M0_RXDV
M0_RXDV
M0_RXDV
M0_RXDV
All
C8
M0_RXD[3]
M0_RXD[3]
M0_RXD[3]
M0_RXD[3]
M0_RXD[3]
M0_RXD[3]
All
C9
M0_RXD[1]
M0_RXD[1]
M0_RXD[1]
M0_RXD[1]
M0_RXD[1]
M0_RXD[1]
All
D1
NC
NC
NC
M1_RXD[1]
M1_RXD[1]
M1_RXD[1]
ZL50118/19/20
D10
M0_RXD[2]
M0_RXD[2]
M0_RXD[2]
M0_RXD[2]
M0_RXD[2]
M0_RXD[2]
All
D11
M0_REFCLK
M0_REFCLK
M0_REFCLK
M0_REFCLK
M0_REFCLK
M0_REFCLK
All
D12
M0_TXD[6]
M0_TXD[6]
M0_TXD[6]
M0_TXD[6]
M0_TXD[6]
M0_TXD[6]
All
D13
M0_TXD[1]
M0_TXD[1]
M0_TXD[1]
M0_TXD[1]
M0_TXD[1]
M0_TXD[1]
All
D14
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
All
D15
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
All
D16
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
D17
M0_ACTIVE_LED
M0_ACTIVE_LED
M0_ACTIVE_LED
M0_ACTIVE_LED
M0_ACTIVE_LED
M0_ACTIVE_LED
All
D18
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
All
D19
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
D20
CPU_DATA[25]
CPU_DATA[25]
CPU_DATA[25]
CPU_DATA[25]
CPU_DATA[25]
CPU_DATA[25]
All
D21
CPU_ADDR[23]
CPU_ADDR[23]
CPU_ADDR[23]
CPU_ADDR[23]
CPU_ADDR[23]
CPU_ADDR[23]
All
D22
CPU_DATA[6]
CPU_DATA[6]
CPU_DATA[6]
CPU_DATA[6]
CPU_DATA[6]
CPU_DATA[6]
All
D2
NC
NC
NC
M1_RXD[0]
M1_RXD[0]
M1_RXD[0]
ZL50118/19/20
D3
NC
NC
NC
M1_RXD[2]
M1_RXD[2]
M1_RXD[2]
ZL50118/19/20
D4
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
D5
NC
NC
NC
M1_RXDV
M1_RXDV
M1_RXDV
ZL50118/19/20
D6
M0_RXER
M0_RXER
M0_RXER
M0_RXER
M0_RXER
M0_RXER
All
D7
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
Ball #
ZL50115
Signal Name
ZL50116
Signal Name
ZL50117
Signal Name
ZL50118
Signal Name
ZL50119
Signal Name
ZL50120
Signal Name
Variant
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)