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參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 529K |
| 代理商： | XQ4005E |
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QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
8
May 19, 1998 (Version 2.1)
XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested.
Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more
precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature). Values apply to all XQ4000E/EX devices unless otherwise noted.
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Note 2: Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Note 1: Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Single Port RAM
Speed Grade
-3
-4
Units
Size
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
T
WCS
T
WCTS
14.4
14.4
15.0
15.0
ns
ns
Clock K pulse width (active edge)
16x2
32x1
T
WPS
T
WPTS
7.2
7.2
7.5
7.5
1 ms
1 ms
ns
ns
Address setup time before clock K
16x2
32x1
T
ASS
T
ASTS
2.4
2.4
2.8
2.8
ns
ns
Address hold time after clock K
16x2
32x1
T
AHS
T
AHTS
0
0
0
0
ns
ns
DIN setup time before clock K
16x2
32x1
T
DSS
T
DSTS
3.2
1.9
3.5
2.5
ns
ns
DIN hold time after clock K
16x2
32x1
T
DHS
T
DHTS
0
0
0
0
ns
ns
WE setup time before clock K
16x2
32x1
T
WSS
T
WSTS
2.0
2.0
2.2
2.2
ns
ns
WE hold time after clock K
16x2
32x1
T
WHS
T
WHTS
0
0
0
0
ns
ns
Data valid after clock K
16x2
32x1
T
WOS
T
WOTS
8.8
10.3
10.3
11.6
ns
ns
Dual-Port RAM
Speed Grade
-3
-4
Units
Size
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
14.4
7.2
2.5
0
1.9
0
2.0
0
7.8
15.0
7.5
2.8
0
2.2
0
2.2
0.3
1 ms
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| XQ4005E-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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| XQ4005E-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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