參數(shù)資料
型號： XQ4005E
廠商： Xilinx, Inc.
英文描述： High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列)
中文描述： 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列）
文件頁數(shù)： 24/34頁
文件大?。?/td> 529K
代理商： XQ4005E
QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
24
May 19, 1998 (Version 2.1)
XQ4028EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000EX devices unless otherwise noted.
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Speed Grade
-4
Units
Description
Size
Symbol
Min
Max
Write Operation
Address write cycle time
16x2
32x1
T
WC
T
WCT
10.6
10.6
ns
ns
Write Enable pulse width (High)
16x2
32x1
T
WP
T
WPT
5.3
5.3
ns
ns
Address setup time before WE
16x2
32x1
T
AS
T
AST
2.8
2.9
ns
ns
Address hold time after end of WE
16x2
32x1
T
AH
T
AHT
1.7
1.7
ns
ns
DIN setup time before end of WE
16x2
32x1
T
DS
T
DST
1.1
1.1
ns
ns
DIN hold time after end of WE
16x2
32x1
T
DH
T
DHT
6.6
6.6
ns
ns
Read Operation
Address read cycle time
16x2
32x1
T
RC
T
RCT
4.5
6.5
ns
ns
Data valid after address change (no
Write Enable)
16x2
32x1
T
ILO
T
IHO
2.2
3.8
ns
ns
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
16x2
32x1
T
ICK
T
IHCK
1.5
3.2
ns
ns
Read During Write
Data valid after WE goes active
(DIN stable before WE)
16x2
32x1
T
WO
T
WOT
6.5
7.4
ns
ns
Data valid after DIN (DIN changes
during WE)
16x2
32x1
T
DO
T
DOT
7.7
8.2
ns
ns
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16x2
32x1
T
WCK
T
WCKT
7.1
9.2
ns
ns
Data setup time before clock K
16x2
32x1
T
DCK
T
DCKT
5.9
8.4
ns
ns
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