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參數資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現場可編程門陣列) |
| 中文描述： | 高可靠性的現場可編程門陣列（高可靠性現場可編程門陣列） |
| 文件頁數： | 18/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
18
May 19, 1998 (Version 2.1)
XQ4028EX DC Characteristics Over Recommended Operating Conditions
Note 1: With up to 64 pins simultaneously sinking 12 mA.
Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND.
XQ4028EX Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Symbol
Description
Min
Max
Units
V
OH
High-level output voltage @ I
OH
= -4.0 mA, V
CC
min
High-level output voltage @ I
OH
= -1.0 mA
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min
(Note 1)
TTL outputs
2.4
V
CMOS outputs
V
CC
-0.5
V
V
OL
TTL outputs
0.4
V
CMOS outputs
0.4
V
V
DR
I
CCO
I
L
Data Retention Supply Voltage (below which configuration data may be lost)
3.0
V
Quiescent FPGA supply current (Note 2)
25
mA
Input or output leakage current
-10
+10
μ
A
C
IN
Input capacitance (sample tested)
Plastic packages
10
pF
Ceramic packages
16
pF
I
RPU
I
RPD
I
RLL
Pad pull-up (when selected) @ V
in
= 0 V (sample tested)
Pad pull-down (when selected) @ V
in
= 5.5 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
0.02
0.25
mA
0.02
0.25
mA
0.3
2.0
mA
Speed Grade
Description
From pad through Global Low Skew buffer, to any clock K
From pad through Global Early buffer, to any clock K in same quadrant
-4
Units
Symbol
T
GLS
T
GE
Max
9.2
5.7
ns
ns
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