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參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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May 19, 1998 (Version 2.1)
13
XQ4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XQ4000E/EX devices unless otherwise noted.
Note 1:
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Note 2:
Speed Grade
Description
Propagation Delays (TTL Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent latch, no delay
-3
-4
Units
Symbol
Device
Min
Max
Min
Max
with delay
T
PID
T
PLI
T
PDLI
All devices
All devices
XQ4005E
XQ4010E
XQ4013E
XQ4025E
2.5
10.8
11.2
3.0
6.0
12.0
12.2
12.6
15.0
ns
ns
ns
ns
ns
ns
Propagation Delays
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Hold Times (Note 1)
Pad to Clock (IK), no delay
with delay
T
IKRI
T
IKLI
All devices
All devices
2.8
4.0
6.8
7.3
ns
ns
T
IKPI
T
IKPID
All devices
All devices
0
0
0
0
ns
ns
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