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參數(shù)資料
| 型號(hào)： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場(chǎng)可編程門陣列（高可靠性現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁數(shù)： | 27/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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May 19, 1998 (Version 2.1)
27
XQ4028EX Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XQ4000EX devices unless otherwise noted
XQ4028EX Global Low Skew Clock, Set-Up and Hold
XQ4028EX Global Early Clock, Set-Up and Hold for IFF
Note 1: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6
ns for BUFGE #s 1, 2, 5 and 6.
XQ4028EX Global Early Clock, Set-Up and Hold for FCL
Note 1: For CMOS input levels, see the
“XQ4028EX Input Threshold Adjustments” on page 27
.
Set-up time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time
Note 2: Under given design conditions. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs.
Use the static timing analyzer to determine the setup and hold times under given design conditions.
Note 3: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2
ns for BUFGE #s 1, 2, 5 and 6.
XQ4028EX Input Threshold Adjustments
The following table must be used to adjust input parameters and input switching characteristics.
Speed Grade
Description
Input Setup Time, using Global Low Skew clock and IFF (full delay)
Input Hold Time, using Global Low Skew clock and IFF (full delay)
IFF = Flip-Flop or Latch
-4
Min
8.0
0
Units
Symbol
T
PSD
T
PHD
ns
ns
Speed Grade
Description
Input Setup Time, using Global Early clock and IFF (partial delay)
Input Hold Time, using Global Early clock and IFF (partial delay)
IFF = Flip-Flop or Latch
-4
Min
6.5
0
Units
Symbol
T
PSEP
T
PHEP
ns
ns
Speed Grade
Description
Input Setup Time, using Global Early clock and FCL (partial delay)
Input Hold Time, using Global Early clock and FCL (partial delay)
FCL = Fast Capture Latch
-4
Min
3.4
0
Units
Symbol
T
PFSEP
T
PFHEP
ns
ns
Speed Grade
Symbol
T
TTLI
T
CMOSI
-4
Units
ns
ns
Description
Max
0
0.3
For TTL input add
For CMOS input add
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