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參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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QPRO
TM
XQ4000E/EX QML High-Reliability Field Programmable Gate Arrays
14
May 19, 1998 (Version 2.1)
XQ4000E IOB Input Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E/EX devices unless
otherwise noted.
Note 1:
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XQ4005E. For other devices see the static timing analyzer.
Note 2:
Note 3:
Speed Grade
Symbol
-3
-4
Units
Description
Device
Min
Max
Min
Max
Setup Times (TTL Inputs)
Pad to Clock (IK),
no delay
with delay
T
PICK
T
PICKD
All devices
XQ4005E
XQ4010E
XQ4013E
XQ4025E
2.6
9.8
10.2
4.0
10.9
11.3
11.8
14.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
(TTL or CMOS)
Clock Enable (EC) to Clock (IK), no delay
with delay
T
ECIK
T
ECIKD
All devices
XQ4005E
XQ4010E
XQ4013E
XQ4025E
2.5
9.7
10.1
3.5
10.4
10.7
11.1
14.0
ns
ns
ns
ns
ns
Global Set/Reset (Note 3)
Delay from GSR net through Q to I1, I2
GSR width
GSR inactive to first active Clock (IK) edge
T
RRI
T
MRW
T
RPO
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4005E
XQ4010E
XQ4013E
XQ4025E
7.8
7.8
11.5
11.5
11.8
11.8
13.0
55.0
70.0
112.0
12.0
21.0
23.0
29.0
15.0
20.3
22.0
28.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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