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參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 3/34頁 |
| 文件大小： | 529K |
| 代理商： | XQ4005E |
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May 19, 1998 (Version 2.1)
3
XQ4000E/EX DC Characteristics Over Operating Conditions
Note 1:
Note 2:
With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with the development system Tie option.
Characterized Only.
*
XQ4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature)
*
**
For plastic package options only.
For ceramic package options only.
Symbol
V
OH
V
OL
I
CCO
I
L
C
IN
I
RIN*
I
RLL*
Description
Min
2.4
Max
Units
V
V
mA
μ
A
pF
mA
mA
High-level output voltage @ I
OH
= -4.0mA, V
CC
min
Low-level output voltage @ I
OL
= 12.0mA, V
CC
min (Note 1) TTL outputs
Quiescent FPGA supply current (Note 2)
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
TTL outputs
0.4
50
+10
16
-0.25
2.5
-10
-0.02
0.2
Speed Grade
Symbol
T
PG
-3
*
Max
-4
**
Max
7.0
11.0
11.5
12.5
7.5
11.5
12.0
13.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Description
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4005E
XQ4010E
XQ4013E
XQ4025E
From pad through Primary buffer, to any
clock K
6.3
6.8
From pad through Secondary buffer, to any
clock K
T
SG
6.8
7.3
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