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參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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May 19, 1998 (Version 2.1)
21
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested.
Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more
precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature). Values apply to all XQ4000EX devices unless otherwise noted.
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Note 2: Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q (XQ4028EX)
Delay from GSR input to any Q (XQ4036EX)
Toggle Frequency )
(for export control purposes)
T
MRW
T
MRQ
T
MRQ
F
TOG
13.0
22.8
24.0
143
ns
ns
ns
MHz
Single Port RAM
Speed Grade
-4
Units
Size
Symbol
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
T
WCS
T
WCTS
11.0
11.0
ns
ns
Clock K pulse width (active edge)
16x2
32x1
T
WPS
T
WPTS
T
ASS
T
ASTS
5.5
5.5
ns
ns
Address setup time before clock K
16x2
32x1
2.7
2.6
ns
ns
Address hold time after clock K
16x2
32x1
T
AHS
T
AHTS
0
0
ns
ns
DIN setup time before clock K
16x2
32x1
T
DSS
T
DSTS
2.4
2.9
ns
ns
DIN hold time after clock K
16x2
32x1
T
DHS
T
DHTS
0
0
ns
ns
WE setup time before clock K
16x2
32x1
T
WSS
T
WSTS
2.3
2.1
ns
ns
WE hold time after clock K
16x2
32x1
T
WHS
T
WHTS
0
0
ns
ns
Data valid after clock K
16x2
32x1
T
WOS
T
WOTS
8.2
10.1
ns
ns
Speed Grade
-4
Units
Description
Symbol
Min
Max
相關(guān)PDF資料 |
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| XQ4013XL-1CB240N | QML High-Reliability FPGAs |
| XQ4000XL | QML High-Reliability FPGAs |
| XQ4013XL-1BG228M | QML High-Reliability FPGAs |
| XQ4013XL-1BG228N | QML High-Reliability FPGAs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XQ4005E-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3BG191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3BG196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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