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參數(shù)資料
| 型號： | XQ4005E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列) |
| 中文描述： | 高可靠性的現(xiàn)場可編程門陣列（高可靠性現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 529K |
| 代理商： | XQ4005E |
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May 19, 1998 (Version 2.1)
7
XQ4000E CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the static timing analyzer and used in the simulator.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XQ4000E/EX devices unless otherwise noted.
Speed Grade
Symbol
-3
-4
Units
Description
Device
Min
Max
Min
Max
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via H1 through H
C inputs via DIN
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Master Set/Reset
Width (High or Low)
T
CKI
T
CKIH
T
CKHH1
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
T
CH
T
CL
4.0
4.0
4.5
4.5
ns
ns
T
RPW
T
RIO
4.0
4.0
5.5
6.5
ns
ns
Delay from Global Set/Reset net to Q
T
MRW
T
MRQ
4005E
4010E
4013E
4025E
4005E
4010E
4013E
4025E
11.5
11.5
18.7
18.7
13.0
55.0
70.0
112.0
23.0
60.0
77.0
134.0
ns
ns
ns
ns
ns
ns
ns
ns
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| XQ4013XL-1CB240N | QML High-Reliability FPGAs |
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| XQ4005E-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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| XQ4005E-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005E-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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