參數(shù)資料
型號(hào): XQ4005E
廠商: Xilinx, Inc.
英文描述: High-Reliability Field Programmable Gate Arrays(高可靠性現(xiàn)場可編程門陣列)
中文描述: 高可靠性的現(xiàn)場可編程門陣列(高可靠性現(xiàn)場可編程門陣列)
文件頁數(shù): 5/34頁
文件大?。?/td> 529K
代理商: XQ4005E
May 19, 1998 (Version 2.1)
5
XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer
(TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E/EX devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Note 1: These delays are specified from the decoder input to the decoder output.
Note 2: Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption
but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
Speed Grade
Symbol
T
WAF
-3
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4005E
XQ4010E
XQ4013E
XQ4025E
Max
Max
9.5
15.0
16.0
18.0
12.5
18.0
19.0
21.0
10.5
16.0
17.0
19.0
12.5
18.0
19.0
21.0
Full length, both pull-ups,
inputs from IOB I-pins
9.0
11.0
Full length, both pull-ups,
inputs from internal logic
T
WAFL
11.0
13.0
Half length, one pull-up,
inputs from IOB I-pins
T
WAO
10.0
12.0
Half length, one pull-up,
inputs from internal logic
T
WAOL
12.0
14.0
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