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參數(shù)資料
| 型號(hào)： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁(yè)數(shù)： | 9/66頁(yè) |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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9
V
RC
4372 I/O Controller
Table 7. Device and Vendor Identification
Bit(s)
Symbol
Name
Functional Description
15:0
VID
Vendor ID
Hardwired to 0x1033 for NEC PCI devices
31:16
DID
Device ID
Hardwired to 0x001A
Table 8. Command Register (PCICMD)
Bit(s)
Symbol
Name
Functional Description
0
IOEN
I/O space enable
Hardwired to 0; ignored
1
MEMEN
Memory space enable
Reset to 0; must set to 1 via software to
enable the V
RC
4372 to respond to
memory space accesses
2
BMAS
Bus master enable
Reset to 0; must be set to 1 to enable the
V
RC
4372 to generate PCI accesses
3
SPC
Special cycles enable
Hardwired to 0; ignored
4
MWI
Memory write and invalidate
enable
Hardwired to 0; ignored
5
VGA
Video Graphics Array
Hardwired to 0; ignored because the
V
RC
4372 is not a VGA device
6
PER
PERR enable
Reset to 0
7
WAIT_CTL
Wait cycle control
Hardwired to 0; ignored
8
SERR_EN
SERR enable
Reset to 0
9
FBBE
Fast back-to-back enable
Hardwired to 0; ignored
15:10
Reserved
Read as 0
Table 9. Status Register (PCISTS)
Bit(s)
Symbol
Name
Functional Description
22:16
Reserved
Read as 0
23
FBBC
Fast back-to-back capable
Hardwired to 1; fast back-to-back enabled
24
DPR
Data parity reported
Data parity reported
26:25
DEVSEL
DEVSEL timing
Hardwired to 01 (medium response)
27
STA
Signaled target abort
Set whenever the V
RC
4372 signals a target
abort
28
RTA
Received target abort
Set whenever the V
RC
4372 master
receives a target abort
29
RMA
Received master abort
Set whenever the V
RC
4372 master
generates a master abort
30
SSE
Signaled system error
Set whenever the V
RC
4372 detects a
system error
31
DPE
Detected parity error
Set whenever the V
RC
4
372 detects a parity
error
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