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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 58/66頁 |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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58
V
RC
4372 I/O Controller
8.0
Error Handling
Table 27 summarizes the causes and effects of various error modes within the
V
RC
4372 controller.
Table 27. Error Handling
Cause
Primary Effects
I/O bus timeout during target access to the
V
RC
4372
Target abort signaled on PCI bus
Target abort signaled error sent to interrupt
controller
Timeout signaled to interrupt controller
I/O bus timeout during master access (DMA)
DMA channel terminates abnormally with flags set
DMA interrupt signaled to interrupt controller
Timeout signaled to interrupt controller
DMA signals master abort on PCI (for example, no
response)
PCI flags set
Master abort interrupt signaled to interrupt
controller
DMA interrupt signaled to interrupt controller
DMA channel terminates abnormally with flags set
DMA receives target abort on PCI
PCI flags set
Target abort received; error signaled to interrupt
controller
DMA interrupt signaled to interrupt controller
DMA channel terminates abnormally with flags set
PCI retry counter expires during DMA
Retry error signaled to interrupt controller
DMA interrupt signaled to interrupt controller
DMA channel terminates abnormally with flags set
The V
RC
4372 senses PERR on PCI during DMA
PERR error flag set in DMA status register
PERR signaled to interrupt controller
DMA channel continues as normal PCI status bits
are set
The V
RC
4372 senses PERR during any valid PCI
access by any master
PERR signaled to interrupt controller; PCI status
bits are set
The V
RC
4372 senses SERR during any valid PCI
access by any master
SERR signaled to interrupt controller; PCI status
bits are set
The V
RC
4372 senses bad parity on address
during a valid PCI access
Claim cycle as though address was correct, but
target abort
Bad address error signaled to interrupt controller
SERR asserted if enabled
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