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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 17/66頁 |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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17
V
RC
4372 I/O Controller
6.3.2
Signal and Pin Descriptions
Symbol
Description
IPL[2:0]
These three, twice-clocked, active-low outputs are the concentrated interrupt
lines to the CPU.
INT[13:0]
These 14 inputs serve as external interrupts to the IPL interrupt pins. Each input
can be programmed to perform as a rising-edge, falling-edge, active-low, or
active-high interrupt.
DMA_INT[3:0]
These four signals originate internally, one from each of the four DMA channels.
They are active low when asserted and are cleared at the DMA channel source.
TICK[1:0]
These two signals originate internally, one from each of the two timer channels.
They are rising-edge when triggered and require clearing within the interrupt
controller, using the INTSTAT write operation.
TOUT_INT
This signal originates internally from the I/O bus time-out block. This signal is
active low when asserted and cleared using the IOTOUT register clearing
mechanism described in Section 6.5.
PERR_INT
This signal originates internally from the PCI bus interface. It is triggered at the
falling edge and requires clearing within the interrupt controller using the
INSTAT write operation. This interrupt source signals that the V
RC
4372 has
sensed that the PCI PERR signal is asserted during a valid PCI transaction
originating from any device on the PCI bus (including V
RC
4372).
SERR_INT
This signal originates internally from the PCI bus interface. It is triggered at the
falling edge and requires clearing within the interrupt controller using the
INSTAT write operation. This interrupt source signals that the V
RC
4372 has
sensed that the PCI SERR signal is asserted during a valid PCI transaction
originating from any device on the PCI bus (including V
RC
4372).
SIG_TA
This signal originates internally from the PCI bus interface. It is triggered at the
falling edge and requires clearing within the interrupt controller using the
INSTAT write operation. This interrupt source signals that the V
RC
4372 has
signalled a PCI
“
Target Abort
”
during a valid PCI target access to V
RC
4372.
REC_TA
This signal originates internally from the PCI bus interface. It is triggered at the
falling edge and requires clearing within the interrupt controller using the
INSTAT write operation. This interrupt source signals that the V
RC
4372 has
received a PCI
“
Target Abort
”
during a valid PCI target access from a DMA
channel.
SIG_MA
This signal originates internally from the PCI bus interface. It is triggered at the
falling edge and requires clearing within the interrupt controller using the
INSTAT write operation. This interrupt source signals that the V
RC
4372 has
signalled a PCI
“
Master Abort
”
during a valid PCI master access from a DMA
channel.
PCI_ADD
This signal originates internally from the PCI bus interface. It is triggered at the
falling edge and requires clearing within the interrupt controller using the
INSTAT write operation. This interrupt source signals that the V
RC
4372 has
detected a parity error on the PCI address bus.
RET_ERR
This signal originates internally from the PCI bus interface. It is triggered at the
falling edge and requires clearing within the interrupt controller using the
INSTAT write operation. This interrupt source signals that the retry counter limit
is reached on a PCI bus cycle originating from a DMA channel.
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