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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 24/66頁 |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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24
V
RC
4372 I/O Controller
6.5
I/O Bus Interface
Controller
6.5.1
Overview
The I/O bus within the V
RC
4372 controller is a mostly demultiplexed ISA-like bus that
controls devices with up to 24 bits of address and up to 16 bits of data. The timing for
I/O bus cycles is provided by the PCI CLK.
The I/O devices controlled by the V
RC
4372 controller are assigned a 256-MB memory
region, located at the address specified by the IOADD register in the PCI header. This
region is further divided into 16 subregions of 16 MB each. The first 10 subregions are
assigned to the chip-select signals CS[9:0]. The next three subregions are assigned to
read and write chip-select pairs CPRD[2:0] and CPWR[2:0]. The remaining three
subregions are reserved for future use. Each subregion can host several external
devices by decoding the lower address bits (starting with A23). To facilitate this
additional decoding, the software should enforce fixed addresses on these lower bits.
Along with these 16 addressable subregions, the I/O bus is also used for DMA
transfers under the control of four DMA channels.
Table 21. Chip-Select Memory Map and Profile Register Assignment
A[27:0]
Chip-Select or
DMA Channel
Profile Register
000 0000
–
0FF FFFF
CS0
IOPROF_00
100 0000
–
1FF FFFF
CS1
IOPROF_01
200 0000
–
2FF FFFF
CS2
IOPROF_02
300 0000
–
3FF FFFF
CS3
IOPROF_03
400 0000
–
4FF FFFF
CS4
IOPROF_04
500 0000
–
5FF FFFF
CS5
IOPROF_05
600 0000
–
6FF FFFF
CS6
IOPROF_06
700 0000
–
7FF FFFF
CS7
IOPROF_07
800 0000
–
8FF FFFF
CS8
IOPROF_08
900 0000
–
9FF FFFF
CS9
IOPROF_09
A00 0000
–
AFF FFFF
CP0
IOPROF_0A
B00 0000
–
BFF FFFF
CP1
IOPROF_0B
C00 0000
–
CFF FFFF
CP2
IOPROF_0C
D00 0000
–
FFF FFFF
Reserved
DMA0
IOPROF_10
DMA1
IOPROF_11
DMA2
IOPROF_12
DMA3
IOPROF_13
Reserved
Note:
No addresses are assigned to the four DMA channels.
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