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參數資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數： | 43/66頁 |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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43
V
RC
4372 I/O Controller
6.6.2
Signal and Pin Descriptions
The I/O bus DMA controller consists of four output, four input, and four bidirectional
pins. All outputs are clocked directly from the rising edge of the PCI CLK signal and do
not float between valid accesses. All output and bidirectional pins have programmable
inversion capabilities controllable through the DMA_OPIN register. The following is a
list of I/O bus DMA controller pin descriptions.
Symbol
Description
DACK[3:0]
These four outputs function as clocked DMA acknowledgments for four DMA
channels. DACK[x] is assigned to DMA channel
“
x
”
. Timing control is individually
programmable via the I/O Profile register (IO_PROF_1x) for the channel and has
timing similar to the chip select pin. At power-up, the default polarity of these
outputs is defined as 1 = deasserted and 0 = asserted.
EOP_TC[3:0]
These four bidirectional pins perform two functions for the four DMA channels: (1)
terminal count output and (2) end of packet input. EOP_TC[x] is assigned to DMA
channel
“
x.
”
At power-up, the pins default to the EOP input function. Each
channel can be individually programmed to use its EOP_TC pin as a TC output
or as an EOP input by setting or clearing the appropriate bit in the DMA_POL
register.
When programmed as an EOP input, the pin can be used by the DMA channel to
terminate the current DMA buffer prematurely. When programmed as a TC
output, the EOP input functionality is not available to the channel and should be
disabled via the EOP_EN bit in the DMAMODE register of the channel.
The EOP (active high) input functionality can be enabled via the EOP_EN bit in
the DMAMODE register for each channel. This EOP input pin, when enabled for
a channel, allows the channel to prematurely terminate either a DMA channel
operation or a DMA channel buffer.
A DMA channel (EMODE set) operation can be terminated regardless of the
state of the RLD bit for the channel. The EOP pin indicates that the current DMA
transfer is the last transfer for the channel. The channel must be reconfigured to
restart data transfers.
A DMA channel buffer (EMODE clear) can be terminated, but still reload the
channel with the next buffer if the RLD bit for the channel is set.
If asynchronous operation for this pin is required, then the pin must be asserted
for a duration of at least two clock periods to allow internal synchronization. More
specifically, if this signal is sampled high during any clock of the valid period, the
packet is terminated after completion of the current transfer. Figure 16 shows an
example of valid EOP assertion.
When EOP_TC[3:0] has been programmed as a TC output, it is asserted instead
of (and at the normal time of) IOA[7:0] during valid I/O bus DMA channel
accesses. It signals the last DMA data transfer of every buffer in a channel
’
s
chain. At all other times, this signal remains deasserted. At power-up, the default
polarity when used as a TC output is defined as: 1 = deasserted and 0 =
asserted.
DREQ[3:0]
Each channel has one DREQ input pin that is used to request a DMA transfer.
Each DREQ may be selected as active high or active low by the D_POL bit in the
channel
’
s DMAMODE register. These inputs are asynchronous; however, for
guaranteed deterministic recognition during contiguous data transfers, they
should meet setup and hold time requirements around the rising edge of CLK
where the I/O bus Turn state is clocked. Refer to the DMA controller descriptions
for more details. Figure 16 depicts the DMA signal relationships.
DMA_INT[3:0]
These four internal signals correspond to each of the DMA channels and provide
an interrupt source to the interrupt controller block within the V
RC
4372 controller.
DMA_INT[3:0] are active-low asserted and are cleared at the DMA channel
source.
This signal can be inverted via programming. Refer to
“
DMA Output Polarity
Control Register: DMAPOL
”
on page 53 for details.
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