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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 8/66頁 |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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8
V
RC
4372 I/O Controller
3.0
PCI Bus Interface Controller
3.1
PCI Configuration
Space Registers
The V
RC
4372 controller implements the 256-byte configuration space defined by the
PCI bus specification (
Table 6
). Access to these registers is accomplished by read and
write accesses in the PCI configuration space. In these modes, onboard logic asserts
the IDSEL signal pin, thus selecting the V
RC
4372 configuration registers. Read
accesses from undefined and reserved locations complete normally and return a logic
0. Undefined or reserved bits also read as logic 0, but the PCI specification requires
that the software not rely on reserved bits having any particular value. Write accesses
to undefined and reserved locations complete normally and the data is discarded.
Table 6. PCI Configuration Registers
Register
Name
Symbol
Configuration
Offset
R/W
Description
Vendor ID
VID
0x01
–
0x00
R
Manufacturer name
Device ID
DID
0x03
–
0x02
R
Device name
Command
PCICMD
0x05
–
0x04
R/W
Coarse control of PCI interface
Status
PCISTS
0x07
–
0x06
R/W
Status information for PCI-related
events
Revision ID
RID
0x08
R
Device revision
Class code
CLASS
0x0b
–
0x09
R
Device type
Cache line size
CLSIZ
0x0c
R/W
System cache line size (words)
Master latency
timer
MLTIM
0x0d
R/W
Value of latency timer for this
master, in PCI clocks
Header type
HTYPE
0x0e
R
Layout for registers in the range
0x10
–
0xff
Register base
address
REGADD
0x13
–
0x10
R/W
Start and size of register
’
s region
I/O bus base
address
IObusADD
0x17
–
0x14
R/W
Start and size of I/O memory
space
Reserved
0x3b
–
0x18
Interrupt line
INTLIN
0x3c
R/W
Interrupt line routing information
Interrupt pin
INTPIN
0x3d
R
Interrupt pin name
Undefined
0x3f
–
0x3e
Disconnect timer
DSCTIM
0x40
R
Not implemented
Retry timer
RTYTIM
0x41
R/W
Maximum number of tries before
terminating transaction. Reset
value = 00
Trdy timer
TDYTIM
0x42
R/W
Not implemented
PCI arbiter
priority control
PAPC
0x43
R/W
Priority scheme for granting the
PCI bus
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