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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 18/66頁 |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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18
V
RC
4372 I/O Controller
6.3.3
Interrupt Controller Registers
Interrupt Polarity Control Register (INTPOL)
This register provides the ability to selectively invert each of the 14 interrupt input pins
(INT[13:0]) before they enter the interrupt controller. The register also provides the
ability to deal with any active polarity or edge type that might be required by an
external peripheral.
Interrupt Trigger Control Register (INTTRIG)
This register provides the ability to selectively trigger on either edge- or level-triggered
interrupts for each of the incoming INT interrupt lines that have passed through the
INTPOL block.
Table 19. Interrupt Controller Registers
Symbol
Offset Value
Reset Value
R/W
Description
INTPOL
0x0203
–
0x0200
0x0000 0000
R/W
INT[13:0] input inversion control
INTTRIG
0x0207
–
0x0204
0x0000 0000
R/W
INT[13:0] level/edge selection
control
INTPINS
0x020b
–
0x0208
N/A
R
Raw input value from each INT pin
INTMSK0
0x020f
–
0x020c
0x0000 0000
R/W
IPL0 mask register
INTSTAT0
0x0213
–
0x0210
0x0000 0000
R/W
IPL0 status register
INTMSK1
0x0217
–
0x0214
0x0000 0000
R/W
IPL1 mask register
INTSTAT1
0x021b
–
0x0218
0x0000 0000
R/W
IPL1 status register
INTMSK2
0x021f
–
0x021c
0x0000 0000
R/W
IPL2 mask register
INTSTAT2
0x0223
–
0x0220
0x0000 0000
R/W
IPL2 status register
Unused
0x02ff
–
0x0224
N/A
R
Read as 0
Bit(s)
Symbol
Description
13:0
INTPOL[13:0]
Each bit corresponds to the INT input pin of the same number.
When a bit is clear, the corresponding INT interrupt input pin is
brought into the controller without inversion to provide the capability
to trigger on either a low level or a rising edge. When a bit is set, the
corresponding input pin is brought into the controller inverted to
provide the ability to trigger on either a high level or a falling edge.
31:14
Unused
Read back as zero
Bit(s)
Symbol
Description
Bits 13:0
INTTRIG[13:0]
Each bit corresponds to the INT input pin of the same number.
When a bit is clear, the corresponding INT interrupt input pin is
level-triggered (active low when the INTPOL bit is set to 0, and
active high when INTPOL is set to 1). When a bit is set, the
corresponding input pin is edge-triggered (rising edge when
INTPOL is set to 0; falling edge when INTPOL is set to 1).
Bits 31:14
Unused
Read back as zero
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