
6
V
RC
4372 I/O Controller
Table 3. I/O Bus Bidirectional/Output Pins
Pin(s)
I/O
Reset
Value
Pull-up/
Pull-down
Max. DC Load
(mA)
AC Load
(pF)
Description
IOA[7:0]
O
Low
Pull-down, 50 K
1
10
–
100
I/O address bus (eight LSB)
IOD[15:8]
IOD[7:0]
I/O
Hi-Z
3
0
–
50
10
–
100
Multiplexed I/O address/data bus
HBE
O
High
1
0
–
30
I/O bus high-byte enable
LBE
O
High
1
0
–
30
I/O bus low-byte enable
ALE
O
High
2
0
–
30
Latches IOA[23:8] from the IOD bus
IOFRAME
O
High
1
0
–
30
Controls the I/O transfer
W_R
O
High
1
0
–
50
I/O write/read status
RD1
RD0
O
High
1
0
–
70
0
–
30
General I/O read strobes
WR1
WR0
O
High
1
0
–
70
0
–
30
General I/O write strobes
BUFOE
O
High
3
0
–
30
I/O data bus buffer enable
CPRD2
CPRD[1:0]
O
High
3
1
0
–
30
0
–
30
Decoded I/O read strobe, 2x F245 load
Decoded I/O read strobes, CMOS load
CPWR2
CPWR[1:0]
O
High
2
1
0
–
30
Decoded I/O write strobe, 3x F373 load
Decoded I/O write strobe, CMOS load
CS[9:8]
CS[7:0]
O
High
3
1
0
–
30
Decoded chip selects, 2x F245 load
Decoded chip selects, CMOS load
IPL[2:0]
O
High
Pull-down, 50 K
1
0
–
15
CPU interrupts
DACK[2:0]
O
High
1
0
–
30
DMA acknowledge
DACK3
O
Low
1
0
–
30
DMA acknowledge
EOP_TC[3:0]
I/O
Hi-Z
1
0
–
30
DMA terminal count and EOP
Table 4. I/O Bus Input Pins
Pin(s)
I/O
Reset Value
Pull-up/Pull-down
Description
IOREADY
I
Pull-down, 50 K
Pull-down, 50 K
Pull-down, 50 K
Ready indicates I/O bus cycle complete
DREQ[3:0]
I
DMA request
INT[13:0]
I/O
(Schmitt)
Hi
–
Z
Interrupt request when SCAN = V
CC
(input only); scan
signals when SCAN = GND (may be input or output)
Table 5. Miscellaneous I/O Pins
Pin(s)
I/O
Reset
Value
Pull-up/
Pull-down
DC
Load
(mA)
AC
Load
(pF)
Description
GPIO[10:0]
I/O
Hi
–
Z
Pull-down, 50 KB
2
(Note)
0
–
30
General-purpose status/control
signals
IOBEEP
O
Low
1
30
Beeper output
SCAN
I
Enables scan test mode when low
TESTOE
I
1
0
Tristates all outputs when low
ARB
I
1
0
Internal arbitration when high;
external arbitration when low