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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 12/66頁 |
| 文件大?。?/td> | 721K |
| 代理商： | VRC4372-1 |
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12
V
RC
4372 I/O Controller
4.0
Control Registers
The V
RC
4372 I/O controller implements 64 KB of control register space (16 KB words).
Beginning at the address specified by the REGADD register in the PCI header and
occupying the lower 64 KB of that address space, the register space is divided into 16
regions of 4096 bytes each and selected by A[15:12]. Each register region is
dedicated to one particular function.
5.0
PCI Interface
The PCI interface performs the following functions:
PCI master
PCI target
Register access
As a PCI master, the PCI interface used by the DMA controller performs memory read
and write cycles on the PCI bus. Burst transfers are executed if the byte count
requested by the DMA channel is greater than four (in multiples of four). Byte
alignment is accomplished in the DMA data buffer section.
As a PCI target, the PCI interface is used for CPU accesses to the I/O bus and should
enforce nonburst accesses by performing a target disconnect on the first word. The
PCI target contains a posted write buffer that allows write cycles to complete with no
PCI bus wait states. When write cycles are executed, data is captured by the posted
write buffer and split into one to four I/O bus accesses, according to the byte enables
and the device data size communicated by the I/O bus controller and as specified by
the profile register for that device. The data is split according to little-endian ordering
and correctly aligned. During splitting of the write data (emptying the I/O bus-posted
write buffer), the target subsection causes the PCI interface to generate a target retry
for all subsequent read or write accesses to the I/O bus.
Register access is also provided by the PCI interface. All V
RC
4372 registers are
accessed as byte-writable 32-bit words directly through this subsection. Register
accesses continue during PCI target-posted, write buffer emptying.
Table 16. Register Allocation
Number
Address Offset
Description
0
0x0000
–
0x0fff
Control registers
0x1000
–
0xffff
Undefined
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