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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 29/66頁 |
| 文件大小： | 721K |
| 代理商： | VRC4372-1 |
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29
V
RC
4372 I/O Controller
IOTOUT (I/O Bus Timeout Control Register)
This register controls the generation of a timeout error condition for regions that are
ready-controlled (in other words, when RDY_on is set to 1 in the corresponding profile
register). If RDY_on = 0, there is no timeout.
The TimeoutCnt field should be written with a value larger than the longest IOREADY-
controlled access period. At every I/O bus access (DMA and regular) to an IOREADY-
controlled region, the TimeoutCnt field is loaded into a counter and decremented on
each rising CLK edge until IOREADY is returned asserted. When IOREADY is
returned asserted, the counter is stopped and no timeout error is generated. If the
counter value reaches zero before IOREADY has been returned asserted, then a
timeout error condition occurs: the I/O bus controller deasserts IOFRAME as if
IOREADY were low, completes the current access, and signals the error on the
TOUT_INT internal signal (Figure 5).
A read cycle from this register resets the timeout condition (ToutERR) and clears the
TOUT_INT signal without affecting the counter.
For additional information about error handling, refer to Section 8.0.
11
BUF_on
When this bit is set, the BUFOE signal is asserted during valid I/O bus
access to the region. When clear, BUFOE is not asserted during
accesses to the region.
15:12
Unused
When read, returns 0
Bit(s)
Symbol
Description
Bit(s)
Symbol
Description
9:0
TimeoutCnt
Number of CLK cycles to timeout
28:10
Unused
Read as 0
29
ArbTmrEn
PCI arbiter delayed retry bit. If this bit is 0, then the arbiter timer
is disabled and the request on the PCI bus is retried
immediately if the I/O bus is not granted immediately. If this bit
is 1, then the PCI request waits four clocks for the I/O bus
before generating a PCI bus retry.
30
ToutEN
Timeout enable. If this bit is set (1), timeout error reporting is
enabled.
31
ToutERR
Timeout error. This bit is set by the hardware when a timeout is
detected and reset by the hardware when the IOTOUT register
is read. ToutERR is updated regardless of the value of ToutEN.
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