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參數(shù)資料
| 型號： | VRC4372-1 |
| 英文描述： | I/O CONTROLLER |
| 中文描述： | I / O控制器 |
| 文件頁數(shù)： | 10/66頁 |
| 文件大小： | 721K |
| 代理商： | VRC4372-1 |
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10
V
RC
4372 I/O Controller
Refer to Section 5.3 for additional information.
Table 10. Revision Identification (RID) and Class Codes
Bit(s)
Symbol
Name
Functional Description
7:0
RID
Revision ID
Hardwired to 0x00
15:8
Prog
Programming interface
Hardwired to 0x00
23:16
SubCl
Subclass
Hardwired to 0x80
31:24
BaseCl
Base class
Hardwired to 0x06
Table 11. Built-In Self Test, Header Type, Master Latency Timer, and Cache Line Size
Bits(s)
Symbol
Functional Description
7:0
CLSIZ
Hardwired to 0x00. The V
RC
4372 rejects cache line fills/
spills (unnatural order bursts).
10:8
MLTIM
Hardwired to 000
15:11
MLTIM
Master Latency Timer. See the PCI specification
(Sections 3.4.4.1 and 6.2.4).
23:16
HTYPE
Hardwired to 0x00
31:24
Reserved
Table 12. Register Base Address (REGADD)
Bits(s)
Symbol
Functional Description
15:0
Reserved
Hardwired to 0x0000; indicates that the V
RC
4372
registers should be located in a 32-bit memory space on
a 64 KB boundary and are not prefetchable
31:16
REGADD
Maps the V
RC
4372 registers in memory on a 64 KB
boundary
Table 13. I/O Memory Base Address (IOADD)
Bits(s)
Symbol
Functional Description
27:0
Reserved
Hardwired to 0x000000 to indicate that the V
RC
4372 I/O
memory should be located in a 32-bit PCI memory
space on a 256-MB boundary and is not prefetchable
31:28
IOADD
The higher four bits of IOADD are used to map the
V
RC
4372 system memory on a 256-MB boundary.
Table 14. Interrupt Pin (INTPIN) and Interrupt Line (INTLIN)
Bit(s)
Symbol
Functional Description
7:0
INTLIN
Provides interrupt line routing information as required by
the PCI specification (Section 6.2.4); can be used as a
scratch pad in motherboard implementations
15:8
INTPIN
Hardwired to 0x01 to indicate that the V
RC
4372 uses
INTA. When the V
RC
4372 is used with add-in cards, this
bit indicates that the V
RC
4372 is connected only to INTA.
When used in a motherboard implementation, the
V
RC
4372 may drive as many as three interrupt lines.
31:16
Undefined
Read as 0
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