參數(shù)資料
型號(hào)： VCT3801A
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video/Controller/Teletext IC Family
中文描述： 視頻/控制/圖文電視IC系列
文件頁數(shù)： 87/172頁
文件大?。?/td> 2243K
代理商： VCT3801A
ADVANCE INFORMATION
VCT 38xxA
Micronas
87
5.3. RAM and ROM
On-chip RAM is composed of static RAM cells. The
RAM will hold all information during reset, as long as
the specified operating voltages are available.
The 64PSDIP Multi Chip Module contains a 128-KByte
Flash EEPROM of the ST M29W010B type. These
devices exhibit electrical Byte program and block erase
functions. Refer to the ST M29W010B data sheet for
details.
5.3.1. Address Map
The following ROM addresses are reserved and can-
not be used to store program code.
A 16-Byte address space is reserved as “Manufacturer
ROM ID”. This area contains a unique ROM ID number
which has to be agreed between Micronas and the
customer. Especially the first 6 digits identify customer
and version. As an example a Micronas demo software
is identified like “MI1108 240700 TV”.
Table 5–2 shows the internal memory segmentation.
Internal program RAM and ROM can be disabled via
the Control Register (chapter 5.4. on page 87). The
internal text RAM can be disabled via Standby Regis-
ter 0 (see page 89).
All memory locations not available internally will be
addressed as external memory. It is possible to oper-
ate with internal and external memory in parallel, but
overlapping memory segments will always be
addressed internally.
During internal memory access, the pins DB0-DB7,
WExQ and OExQ are tristate. For emulation and test
purposes it is possible to change this behavior via the
5.3.2. Bootloader
A segment of the internal ROM is reserved for boot-
loader code. Via this bootloader code it is possible to
download additional code into the internal RAM and
execute this code. The downloaded code can be used
to program the external Flash EEPROM.
After reset the bootloader checks the I
2
C bus pins SDA
and SCL for a special identification sequence. If no
identification sequence is detected, the bootloader
starts the application program code.
The bootloader checks the address FFD6/FFD7 of the
external memory if there is a predefined pattern
(A55Ah). If so, it starts the external application soft-
ware else it starts the internal application software.
5.4. Control Register
The Control Register CR serves to configure the ways,
by which certain system resources are accessed dur-
ing operation. The main purpose is to obtain a variable
system configuration during IC test.
Upon each High transition on the RESQ pin internal
hardware reads data from address location 00FFF9h
and stores it to the CR. The state of the TEST pin at
this timepoint specifies which program storage source
is accessed for this read:
– With the TEST pin Low, the control byte is read from
internal program storage (mask ROM). With location
00FFF9h set to FFh, this is the setting for stand-
alone operation.
– With the TEST pin High, the control byte is read
from external memory via the test bus (for test pur-
poses only).The system will thus start up according
to the configuration defined in address location
00FFF9h and automatically copied to register CR.
Table 5–1:
Reserved (physical) addresses
Addresses
Usage
00FFC6
00FFD5
Manufacturer ROM ID
00FFD6
00FFD7
reserved for bootloader
00FFD8
00FFF7
Interrupt Vectors
00FFF8
reserved
00FFF9
Control Word (during reset)
00FFFA
00FFFB
NMI Vector (expanded by
Interrupt Controller)
00FFFC
00FFFD
Reset Vector
0xFFFE
0xFFFF
IRQ/BRK Vector
Table 5–2:
Internal Memory Locations
Addresses
Internal Memory
000000
000FFF
4k Program RAM
001E00
001FFF
I/O
Register
002000
0023FF
1k Bootloader ROM
002400
019FFF
95k Program ROM
0A0000
0A3FFF
16k Text RAM
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