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VCT 38xxA
ADVANCE INFORMATION
40
Micronas
Table 2–5:
Control registers of the Fast Processor for control of the video front-end functions
default values are initializied at reset
FP Sub-
address
Function
Default
Name
Standard Selection
h’20
Standard select:
bit[2:0]
standard
0
1
2
3
4
5
6
7
0/1
PAL B,G,H,I (50 Hz)
NTSC M
SECAM
NTSC44
PAL M
PAL N
PAL 60
NTSC COMB (60 Hz)
standard modifier
PAL modified to simple PAL
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
reserved (set to 0)
0/1
2-H comb filter off/on
0/1
S-VHS mode off/on (2-H comb is switched off)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
3.579545
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
bit[3]
bit[4]
bit[5]
bit[6]
Option bits allow to suppress parts of the initialization, this can be used
for color standard search:
bit[7]
bit[8]
bit[9]
bit[10]
no hpll setup
no vertical setup
no acc setup
2-H comb filter set-up only
bit[11]
status bit, normally write 0. After the FP has switched to a
new standard, this bit is set to 1 to indicate operation
complete. Standard is automatically initialized when the
insel register is written.
0
SDT
PAL
NTSC
SECAM
NTSC44
PALM
PALN
PAL60
NTSCC
SDTMOD
COMB
SVHS
SDTOPT
h’148
Enable automatic standard recognition (ASR)
bit[0]
0/1
PAL B,G,H,I
bit[1]
0/1
NTSC M
bit[2]
0/1
SECAM
bit[3]
0/1
NTSC44
bit[4]
0/1
PAL M
bit[5]
0/1
PAL N
bit[6]
0/1
PAL 60
bit[10:7] reserved set to 0
bit[11]
1
reset status information ‘switch’ in asr_status
(cleared automatically)
(50 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
0: disable recognition; 1: enable recognition
Note: For correct operation don’t change FP reg. 20h and 21h, while
ASR is enabled!
0
ASR_ENA