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參數資料
| 型號： | VCT3801A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video/Controller/Teletext IC Family |
| 中文描述： | 視頻/控制/圖文電視IC系列 |
| 文件頁數： | 117/172頁 |
| 文件大?。?/td> | 2243K |
| 代理商： | VCT3801A |
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ADVANCE INFORMATION
VCT 38xxA
Micronas
117
5.14.3.1.14. Capture and Input Action
The Input Action logic operates independently of the
Output Action logic and is triggered by an external
input in a way defined by field CCxM.IAM. Following
Table 5–18 it can completely ignore events, trigger on
rising or falling edge or on both edges. When trig-
gered, the following actions take place:
– Flag CCxI.CAP is set.
– The CCxOR interrupt source is triggered when acti-
vated.
– The 16-bit capture register CCx stores the current
CCC value, i.e. the “time” of the external event.
Read CCx Low byte first. Further compare action
will be locked until the subsequent High byte read is
completed. Thus a coherent result is ensured, no
matter how much time has elapsed between the two
reads.
Some applications suffer from fast input bursts and a
lot of capture events and interrupts in consequence. If
the SW cannot handle such a rate of interrupts, this
could evoke stack overflow and system crash. To pre-
vent such fatal situations the Lock After Capture (LAC)
mode is implemented. If bit CCxI.LAC is set, only one
capture event will pass. After this event has triggered a
capture, the Input Action logic will lock until it is
unlocked again by writing an arbitrary value to register
CCxM. Make sure that this write only restores the
desired setting of this register.
Programming the Input Action logic while an input tran-
sition occurs may result in an unexpected triggering.
This may overwrite the capture register, lock the Input
Action logic if in LAC mode and generate an interrupt.
Make sure that SW is prepared to handle such a situa-
tion.
For testing purposes, a permanent reset (FFFFh) may
be forced on capture register CCx by setting bit
CCxI.RCR. Make sure that the reset is only temporary.
5.14.3.1.15. Interrupts
Each SU supplies two internal interrupt events:
1. Input Capture event and
2. Comparator equal state.
As previously explained, interrupt events will set the
corresponding flags in register CCxI. In addition to the
above mentioned two, the CCC Overflow interrupt
event sets flag CCxI.OFL in each SU. Thus, three
interrupt events are available in each SU. The corre-
sponding flags are masked with their mask bits in reg-
ister CCxM and passed to a logical or. The result
(CCxOR) is fed to the Interrupt Controller as a first
interrupt source. In addition, the Comparator equal
(CCxCOMP) interrupt is directly passed to the Inter-
rupt Controller as second interrupt source. Thus a SU
offers four types of interrupts: CCC overflow (maskable
ored), input capture event (maskable ored) and com-
parator equal state (maskable ored and non-maskable
direct).
All interrupt sources act independently, parallel inter-
rupts are possible. The interrupt flags enable SW to
determine the interrupt source and to take the appro-
priate action. Before returning from the interrupt rou-
tine the corresponding interrupt flag should thus be
cleared by writing a 1 to the corresponding bit location
in register CCxI.
The interrupts generated by internal logic (CCC Over-
flow and Comparator equal) will trigger in a predeter-
mined and known way. But as explained in 5.14.3.1.14.
erroneous input signals may cause some difficulties
concerning the Input Capture input, as well, as inter-
rupt handling. To overcome possible problems the
Input Capture Interrupt flag CCxI.CAP is double buff-
ered. If a second or even more input capture interrupt
events occur before the interrupt flag is cleared (i.e.
SW was not able to keep track), the flag goes to a third
state. Two consecutive writes to this bit in register CCxI
are then necessary to clear the flag. This enables SW
to detect such a multiple interrupt situation and eventu-
ally to discard the capture register value which always
relates to the latest input capture event and interrupt.
The internal CAPCOM module control logic always
runs on the oscillator frequency, regardless of CPU
Slow mode. Avoid write accesses to the CCxI register
in CPU Slow mode, since the logic would interpret one
CPU access as many consecutive accesses. This may
yield unexpected results concerning the functionality of
the interrupt flags. The following procedure should be
followed to handle the capture interrupt flag CAP:
1. SW responds to a CAPCOM interrupt, switching to
CPU Fast mode if necessary and determining that
the source is a capture interrupt (CAP flag =1).
2. The interrupt service routine is processed.
3. Just before returning to main program, the service
routine acknowledges the interrupt by writing a 1 to
flag CAP.
4. The service routine reads CAP again. If it is reset,
the routine can return to main program as usual. If it
is still set an external capture event overrun has
happened. Appropriate actions may be taken (i.e.
discarding the capture register value etc.).
5. go to 3.
5.14.4.Inactivation
The CAPCOM module is inactivated and returned to
standby mode (power down mode) by setting the
Enable bit to 0. Section 5.14.2. applies. CCxI and
CCxM are only reset by system reset, not by standby
mode.
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