參數(shù)資料
型號： VCT3801A
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video/Controller/Teletext IC Family
中文描述： 視頻/控制/圖文電視IC系列
文件頁數(shù)： 113/172頁
文件大?。?/td> 2243K
代理商： VCT3801A
ADVANCE INFORMATION
VCT 38xxA
Micronas
113
5.13.Timer T0 and T1
Timer T0 and T1 are 16-bit auto reload down counters.
They serve to deliver a timing reference signal, to out-
put a frequency signal or to produce time stamps.
5.13.1.Features
– 16-bit auto reload counter
– Time value readable
– Interrupt source output
– Frequency output
Fig. 5–22:
Block diagram of timer T0 and T1
5.13.2.Operation
The timer’s 16-bit down-counter is clocked by the input
clock and counts down to zero. Reaching zero, it gen-
erates an output pulse, reloads with the content of the
TIMx reload register and restarts its travel.
T0 and T1 are not affected by CPU Slow mode.
The clock input frequency can be selected from three
possible values by programming the timer mode regis-
ter TIMxM.CSF. After reset, both timers are in standby
mode (inactive).
Prior to entering active mode, proper SW initialization
of the Ports assigned to function as Tx-OUT outputs
has to be made. The ports have to be configured Spe-
cial Out (see Section 5.18. on page 126).
To initialize a timer, Reload register TIMx has to set to
the desired time value, still in standby mode. For enter-
ing active mode, set the corresponding enable bit in
the Standby register. The timer will immediately start
counting down from the time value present in register
TIMx.
During active mode, a new time value is loaded by writ-
ing to the 16-bit register TIMx, High byte first. Upon
writing the Low byte, the reload register is set to the
new 16-bit value, the counter is reset, and immediately
starts down-counting with the new value.
On reaching zero, the counter generates a reload sig-
nal, which can be used to trigger an interrupt. The
same signal is connected to a divide by two scaler to
generate the output signal Tx-OUT with a pulse duty
factor of 50 %.
The interrupt source output of this module is routed to
the Interrupt Controller logic (see Section 5.10. on
page 99).
The state of the down-counter is readable by reading
the 16-bit register TIMx, Low byte first. Upon reading
the Low byte, the High byte is saved to a temporary
latch, which is then accessed during the subsequent
High byte read.
Thus, for time stamp applications, read consistency
between Low and High byte is guaranteed.
Returning a timer to standby mode by resetting the
corresponding Enable bit will halt its counter and will
set its output to Low. The register TIMx remains
unchanged.
1/2
16
zero
16 bit Auto-reload
Down counter
Reload-reg.
TIM x
w
r
TIM x
Tx
Interrupt
Source
clk
Tx-OUT
3:1
MUX
f
OSC
/2
1
f
OSC
/2
9
f
OSC
/2
17
2
TIMxM.CSF
SR1.TIMx
0
1
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