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參數(shù)資料
| 型號： | VCT3801A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video/Controller/Teletext IC Family |
| 中文描述： | 視頻/控制/圖文電視IC系列 |
| 文件頁數(shù)： | 82/172頁 |
| 文件大?。?/td> | 2243K |
| 代理商： | VCT3801A |
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VCT 38xxA
ADVANCE INFORMATION
82
Micronas
3.14.I
2
C-Bus Slave Interface
Communication between the TPU and the TV control-
ler is done via I
2
C bus. For detailed information on the
I
2
C bus please refer to the Philips manual ‘I
2
C bus
Specification’.
The TPU acts as a slave transmitter/receiver and uses
clock synchronization to slow down the data transfer if
necessary. General call address will not be acknowl-
edged.
Different memories and functions of TPU can be
accessed by subaddressing. The byte following the
slave address byte is defined as the subaddress byte.
Maximum length of an I
2
C telegram is 256 Bytes fol-
lowing slave address and subaddress byte. The inter-
face supports data transfer with autoincrement.
The I
2
C bus interface is interrupt-driven and uses an
internal 48-Byte buffer to collect I
2
C data in real-time
without disturbing internal processes. This is done to
avoid clock synchronization as far as possible. When
the TPU has to process the I
2
C buffer and the I
2
C tele-
gram has not yet been stopped, the I
2
C clock line will
be held down.
The time required to process the I
2
C buffer depends
on other processes running inside the TPU firmware.
Thus the following I
2
C telegram addressing the TPU
can be held after the slave address byte until the old
telegram is completely processed.
3.14.1.Subaddressing
Access to all memory locations and to the command
interface is achieved by subaddressing. Both the exter-
nal DRAM and the internal CPU memory can be
addressed completely. The TPU acknowledges 6 dif-
ferent subaddresses following the slave address (see
Table 3–17 on page 82).
The following symbols are used to describe the I
2
C
example telegrams:
<
>
ab
ah
al
cc
dd
ss
..
start condition
stop condition
address bank byte
address high byte
address low byte
command byte
data byte
status byte
0
n continuation bytes
3.14.1.1. CPU Subaddressing
There are 2 CPU subaddresses to access CPU mem-
ory: either with static memory address or with autoin-
crementing memory address. The main purpose of
CPU subaddressing is to write text into the OSD buffer
and to access the I/O page (see Section 3.13. on
page 76). The static CPU subaddress can be used to
write more than 1 Byte into the same I/O page register.
The CPU subaddress has to be followed by 2 address
bytes defining the CPU memory address. The follow-
ing data byte is written into this address. In the case of
autoincrement the continuation bytes are written into
incrementing memory addresses.
Table 3–17:
I
2
C bus subaddresses
Name
Binary Value
Hex Value
Mode
Function
TPU
0010 001x
22, 23
W, R
TPU slave address
Sub 1
0111 1000
78
W
subaddressing CPU (static)
Sub 2
0111 1001
79
W
subaddressing CPU (autoincrement)
Sub 3
0111 1010
7A
W
subaddressing DRAM (autoincrement)
Sub 4
0111 1011
7B
W
subaddressing command language
Data
0111 1100
7C
R/W
subaddressing data register
Status
0111 1101
7D
R
status register
bit 7 = command wait
bit 6 = command invalid
bit 5 = command found no data
bit 4 = not used
bit 3 = not used
bit 2 = not used
bit 1 = 0
bit 0 = 0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VCT3802A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3803A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3804A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3811A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3831A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
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