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參數(shù)資料
| 型號(hào)： | VCT3801A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video/Controller/Teletext IC Family |
| 中文描述： | 視頻/控制/圖文電視IC系列 |
| 文件頁(yè)數(shù)： | 32/172頁(yè) |
| 文件大小： | 2243K |
| 代理商： | VCT3801A |
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VCT 38xxA
ADVANCE INFORMATION
32
Micronas
2.15.I
2
C Bus Slave Interface
Communication between the VDP and the TV control-
ler is done via I
2
C bus. For detailed information on the
I
2
C bus please refer to the Philips manual ‘I
2
C bus
Specification’.
The VDP has two I
2
C bus slave interfaces (for compat-
ibility with VPC/DDP applications)
one in the
front-end and one in the back-end. Both I
2
C bus inter-
faces use I
2
C clock synchronization to slow down the
interface if required. Both I
2
C bus interfaces use one
level of subaddress: the I
2
C bus chip address is used
to address the VDP and a subaddress selects one of
the internal registers. The I
2
C bus chip addresses are
given below:
The registers of the VDP have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
Fig. 2–26 shows I
2
C bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
2.15.1.Control and Status Registers
Table 2–3 gives definitions of the VDP control and sta-
tus registers. The number of bits indicated for each
register in the table is the number of bits implemented
in hardware, i.e. a 9-bit register must always be
accessed using two data bytes but the 7 MSB will be
‘don’t care’ on write operations and ‘0’ on read opera-
tions. Write registers that can be read back are indi-
cated in Table 2–3.
Functions implemented by software in the on-chip con-
trol microprocessor (FP) are explained in Table 2–5.
A hardware reset initializes all control registers to 0.
The automatic chip initialization loads a selected set of
registers with the default values given in Table 2–3.
The register modes given in Table 2–3 are
– w:
write only register
– w/r:
write/read data register
– r:
read data from VDP
– v:
register is latched with vertical sync
– h:
register is latched with horizontal
Fig. 2–26:
I
2
C bus protocols
Table 2–2:
I
2
C chip addresses
Chip
Address
A6
A5
A4
A3
A2
A1
A0
R/W
front-end
1
0
0
0
1
1
1
1/0
back-end
1
0
0
0
1
0
1
1/0
P
S
1
0
SDA
SCL
S
S
1000 111
1000 111
W Ack
Ack
W
0111 1100
0111 1100
Ack
Ack
S
1 or 2 byte Data
1000 111
R
high byte Data
low byte Data
P
W
R
Ack
Nak
S
P
=
=
=
=
=
=
0
1
0
1
Start
Stop
Ack
Nak P
I
2
C write access
subaddress 7c
I
2
C read access
subaddress 7c
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| VCT3802A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3803A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3804A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3811A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3831A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
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