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VCT 38xxA
ADVANCE INFORMATION
102
Micronas
IPF0 to 7
r1:
r0:
w:
Interrupt Pending Flag of Input 0 to 7
No interrupt is pending.
Interrupt is pending.
Current request is finished.
For interrupt pending flags 8 to 15 refer to description
of register IRP.
A write access to this memory location signals to the
Interrupt Controller that the current request has been
served.
PRIOn
r:
Priority of interrupt input n
Priority of the corresponding interrupt
input.
Priority of the corresponding interrupt
input.
w:
Priority zero prevents the Interrupt Controller from
being triggered but the pending register is not affected.
All incoming requests are stored in the pending regis-
ters. With two inputs having the same PRIO setting,
the higher numbered input has priority.
Table 5–7:
Single interrupt service
DAINT
A1INT
Resulting Function
0
1
Disable after current interrupt.
0
0
Serve one interrupt request.
1
x
Normal interrupt mode.
118:
1F21
119:
IRRET
120:
Interrupt Return Register
bit
7
6
5
4
3
2
1
0
r
IPF7
IPF6
IPF5
IPF4
IPF3
IPF2
IPF1
IPF0
w
A write access signals the Interrupt Controller that the current request has
been served.
reset
0
0
0
0
0
0
0
0
121:
1F22
122:
IRPRI10
123:
Interrupt Priority Register, Input 0
and 1
bit
7
6
5
4
3
2
1
0
r/w
PRIO1
PRIO0
reset
0
0
0
0
0
0
0
0
124:
1F23
125:
IRPRI32
126:
Interrupt Priority Register, Input 2
and 3
bit
7
6
5
4
3
2
1
0
r/w
PRIO3
PRIO2
reset
0
0
0
0
0
0
0
0
127:
1F24
128:
IRPRI54
129:
Interrupt Priority Register, Input 4
and 5
bit
7
6
5
4
3
2
1
0
r/w
PRIO5
PRIO4
reset
0
0
0
0
0
0
0
0
130:
1F25
131:
IRPRI76
132:
Interrupt Priority Register, Input 6
and 7
bit
7
6
5
4
3
2
1
0
r/w
PRIO7
PRIO6
reset
0
0
0
0
0
0
0
0
133:
1F26
134:
IRPRI98
135:
Interrupt Priority Register, Input 8
and 9
bit
7
6
5
4
3
2
1
0
r/w
PRIO9
PRIO8
reset
0
0
0
0
0
0
0
0
136:
1F27
137:
IRPRIBA
138:
Interrupt Priority Register, Input
10 and 11
bit
7
6
5
4
3
2
1
0
r/w
PRIO11
PRIO10
reset
0
0
0
0
0
0
0
0
139:
1F28
140:
IRPRIDC
141:
Interrupt Priority Register, Input
12 and 13
bit
7
6
5
4
3
2
1
0
r/w
PRIO13
PRIO12
reset
0
0
0
0
0
0
0
0
142:
1F29
143:
IRPRIFE
144:
Interrupt Priority Register, Input
14 and 15
bit
7
6
5
4
3
2
1
0
r/w
PRIO15
PRIO14
reset
0
0
0
0
0
0
0
0
Table 5–8:
PRIOn usage
PRIOn
Resulting Function
0h
Interrupt input is disabled
1h
Interrupt input is enabled with lowest priority
:
:
Fh
Interrupt input is enabled with highest priority