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參數(shù)資料
| 型號(hào)： | VCT3801A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video/Controller/Teletext IC Family |
| 中文描述： | 視頻/控制/圖文電視IC系列 |
| 文件頁(yè)數(shù)： | 109/172頁(yè) |
| 文件大小： | 2243K |
| 代理商： | VCT3801A |
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ADVANCE INFORMATION
VCT 38xxA
Micronas
109
5.12.I
2
C-Bus Master Interface
The I
2
C bus interface is a pure Master system, Multi-
master busses are not realizable. The clock and data
terminal pins have open-drain outputs.
The I
2
C bus master interface can operate on two termi-
nals. Terminal 1 is connected to the pins SDA/SCL,
terminal 2 can be connected either to the pins
P36/P37 or to the pins P22/P23. Please refer to chap-
ter 5.18. on page 126 how to set up the corresponding
port pins.
The I
2
C bus master interface is not affected by CPU
Slow mode.
The bit rate is programmable using a clock prescaler.
A complete telegram is assembled by the software out
of individual sections. Each section contains an 8-bit
data. This data is written into one of the six possible
Write registers. Depending on the chosen address, a
certain part of an I
2
C bus cycle is generated. By
means of corresponding calling sequences it is there-
fore possible to join even very long telegrams (e.g.
long data files for auto increment addressing of I
2
C
slaves).
The software interface contains a 5 word deep Write-
FIFO for the control data registers, as well, as a 3 word
deep Read FIFO for the received data. Thus most of
the I
2
C telegrams can be transmitted to the hardware
without the software having to wait for empty space in
the FIFO.
An interrupt is generated on two conditions:
– The Write-FIFO was filled and reaches the ‘half full’
state.
– The Write-FIFO is empty and stop condition is com-
pleted.
All address and data fields appearing on the bus are
constantly monitored and written into the Read-FIFO.
The software can then check these data in comparison
with the scheduled data. If a read instruction is han-
dled, the interface must set the data word FFH, so that
the responding slave can insert its data. In this case
the Read-FIFO contains the read-in data.
If telegrams longer than 3 bytes (1 address, 2 data
bytes) are received, the software must check the filling
condition of the Write-FIFO and, if necessary, fill it up
(or read out the Read-FIFO). A variety of status flags is
available for this purpose:
– The ‘half full’ flag I2CRS.WFH is set if the Write-
FIFO is filled with three bytes.
– The ‘empty’ flag I2CRS.RFE is set if there is no
more data available in the Read-FIFO.
– The ‘busy’ flag I2CRS.BUSY is activated by writing
any byte to any one of the Write registers. It stays
active until the I
2
C bus activities are stopped after
the stop condition generation.
Moreover, the ACK-bit is recorded separately on the
bus lines for the address and the data fields. However,
the interface itself can set the address ACK=0. In any
case the two ACK flags show the actual bus condition.
These flags remain until the next I
2
C start condition is
generated.
For example, the software has to work off the following
sequence (ACK
=
1) to read a 16-bit word from an I
2
C
device address 10H (on condition that the bus is not
active):
– write 021H to
I2CWS0
– write 0FFH to
I2CWD0
– write 0FFH to
I2CWP0
– read RFE bit from
I2CRS
– read dev. address from I2CRD
– read RFE bit from
I2CRS
– read 1st data byte from I2CRD
– read RFE bit from
I2CRS
– read 2nddata byte from I2CRD
The value 21H in the first step results from the device
address in the 7 MSBs and the R/W-bit (read=1) in the
LSB. If the telegrams are longer, the software has to
ensure that neither the Write-FIFO nor the Read-FIFO
can overflow.
– To write data to this device:
– write 20H to
I2CWS0
– write 1st databyte to
I2CWD0
– write 2nddatabyte to
I2CWP0
The bus activity starts immediately after the first write
to the Write-FIFO. The transmission can be synchro-
nized by an artificial extension of the Low phase of the
clock line. Transmission is not continued until the state
of the clock line is High once again. Thus, an I
2
C slave
device can adjust the transmission rate to its own abili-
ties.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VCT3802A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3803A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3804A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3811A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
| VCT3831A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video/Controller/Teletext IC Family |
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