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| 型號： | V62C5181024LL-70P |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70% |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 7/43頁 |
| 文件大小： | 1155K |
| 代理商： | V62C5181024LL-70P |
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K4S643232C
CMOS SDRAM
REV. 1.1 Nov. '99
- 7 -
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
50pF
*1
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
*1
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
1. The DC/AC Test Output Load of K4S643232C-55/60/70 is 30pF.
2. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V.
Note :
OPERATING AC PARAMETER
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
Note :
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
-70
3
7
2
3
3
7
100
Unit
Note
-55
-60
-80
-10
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
CL
3
2
-
3
6
2
-
2
-
3
8
2
3
10
2
CLK
ns
CLK
CLK
CLK
CLK
us
t
CC(min)
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
5.5
10
12
1
1
1
1
3
3
7
-
-
-
3
3
7
-
-
-
-
-
-
3
3
6
2
2
5
2
2
5
2
2
4
Row active time
Row cycle time
t
RC
(
min
)
10
-
10
-
10
-
9
7
7
6
CLK
1
Row cycle time in Auto refresh
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
t
RFC
(
min
)
t
RDL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
t
MRS(min)
12
-
12
-
10
-
9
7
7
6
CLK
CLK
CLK
CLK
CLK
CLK
1,6
2,
5
2
2
2
1
1
1
2
2
1
Number of valid output data
CAS Latency=3
CAS Latency=2
ea
4
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