參數(shù)資料
型號(hào): V62C5181024LL-70P
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70%
中文描述: 200萬(wàn)× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL
文件頁(yè)數(shù): 34/43頁(yè)
文件大小: 1155K
代理商: V62C5181024LL-70P
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CMOS SDRAM
K4S643232C
REV. 1.1 Nov. '99
- 34
Read & Write Cycle with Auto Precharge II @Burst Length=4
HIGH
Row Active
(A-Bank)
: Don't care
*Note:
* When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .
- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Row Active
(B-Bank)
Read with
Auto Pre
charge
(A-Bank)
Write with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
BA
0
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Qa0
Qa1
Qb0
Qb1
Qa0
Qa1
Qb0
Qb1
Ra
Rb
Ca
Ra
Rb
Ra
Cb
Qb2
Qb3
Read without Auto
precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank)*
Precharge
(B-Bank)
Da0
Da1
Da0
Da1
Qb2
Qb3
Ca
Ra
BA
1
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