參數(shù)資料
型號(hào): V62C5181024LL-70P
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70%
中文描述: 200萬(wàn)× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL
文件頁(yè)數(shù): 39/43頁(yè)
文件大?。?/td> 1155K
代理商: V62C5181024LL-70P
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CMOS SDRAM
K4S643232C
REV. 1.1 Nov. '99
- 39
Burst Read Single bit Write Cycle @Burst Length=2
HIGH
Row Active
(A-Bank)
Row Active
(C-Bank)
Write with
Auto Precharge
(B-Bank)
: Don't care
*Note :
1. BRSW modes is enabled by setting A
9
"High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that t
RAS
should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
Write
(A-Bank)
*Note 1
Row Active
(B-Bank)
Read
(C-Bank)
Read with
Auto Precharge
(A-Bank)
Precharge
(C-Bank)
*Note 2
BA
0
BA
1
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
DAa0
DAa0
QAb0
QAb1
QAb0
QAb1
DBc0
DBc0
QCd0
QCd1
QCd0
QCd1
RAa
CAa
RBb
CAb
RCc
CBc
CCd
RAc
RAa
RBb
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