參數(shù)資料
型號(hào): V62C5181024LL-70P
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70%
中文描述: 200萬(wàn)× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL
文件頁(yè)數(shù): 40/43頁(yè)
文件大?。?/td> 1155K
代理商: V62C5181024LL-70P
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CMOS SDRAM
K4S643232C
REV. 1.1 Nov. '99
- 40
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
Precharge
Power-down
Entry
: Don
t Care
*Note :
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tss prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
*Note 1
Precharge
tSS
*Note 2
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
tSS
tSS
Ra
Ca
Ra
Qa0
Qa1
Qa2
Row Active
Precharge
Power-down
Exit
Active
Power-down
Entry
Active
Power-down
Exit
Read
tSHZ
*Note 3
*Note 2
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