參數資料
型號: V62C5181024LL-70P
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70%
中文描述: 200萬× 32內存為512k × 32 × 4銀行同步DRAM LVTTL
文件頁數: 3/43頁
文件大?。?/td> 1155K
代理商: V62C5181024LL-70P
K4S643232C
CMOS SDRAM
REV. 1.1 Nov. '99
- 3 -
The K4S643232C is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle
GENERAL DESCRIPTION
FEATURES
512K x 32Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
Part NO.
K4S643232C-TC/L55
K4S643232C-TC/L60
K4S643232C-TC/L70
K4S643232C-TC/L80
K4S643232C-TC/L10
Max Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
Interface
Package
LVTTL
86
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 32
512K x 32
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
512K x 32
512K x 32
Timing Register
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