參數(shù)資料
型號: V62C5181024LL-70P
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70%
中文描述: 200萬× 32內存為512k × 32 × 4銀行同步DRAM LVTTL
文件頁數(shù): 38/43頁
文件大小: 1155K
代理商: V62C5181024LL-70P
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CMOS SDRAM
K4S643232C
REV. 1.1 Nov. '99
- 38
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
Row Active
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
Write
(A-Bank)
*Note 2,4
tBDL
*Note :
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC
parameter of t
RDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency.
HIGH
tRDL
BA
0
BA
1
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
RAa
CAa
CAb
RAa
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